Mikio Ashikawa

Novel high density, stacked capacitor MOS RAM

A novel one transistor type MOS RAM cell is successfully developed and achieves a higher degree of integration than realized to date with conventional RAMs. This cell provides remarkable area reduction and/or an increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor. It is called a stacked capacitor RAM (STC RAM) cell. This new cell has a triple level poly-Si structure of poly-Si word lines and Al bit lines. The stacked capacitor is composed of a poly-Si - Si3N4- poly-Si structure. A 256 bit STC MOS RAM is fabricated with 3 µm technology and operates successfully. The STC RAM cell area, 52.5 µm2, is remarkably smaller than the cell area of conventional RAMs with double level poly-Si gate structure, 160 µm2.

An NPN structure 484×384 MOS imager for a single-chip color camera

An MOS imager featuring an NPN structure for anti blooming and built-in double video lines for color signal pickup will be described. Imager is used in single-chip color camera with TV resolution.

Silicon Planar Devices Using Nitrogen Ion Implantation

Nitrogen implanted polycrystalline silicon layers are used as an oxidation mask in place of conventional silicon nitride layers for the fabrication of planar structured MOS FETs. The stress effect and anomalous oxidation behavior arising from the conventional LOCOS process are thoroughly eliminated. Moreover, the lateral oxidation effect under the oxidation mask was sufficiently reduced. The threshold voltage, unit channel conductance and junction leakage current of devices having nitrogen implanted polycrystalline silicon gates are on the same level as those of conventional LOCOS type devices, which indicates that heavily implanted nitrogen has no effect on the degradation of the substrate crystal. It is also found that silicon dioxide layers behave as diffusion masks against electrically active nitrogen. Another distinct merit of this process is the elimination of the mask alignment margin between the active region and the polycrystalline silicon gate, which makes possible the consequent increase in the device packing density. These results confine the applicability of this process technology to the fabrication of MOS LSIs with a high packing density.

Substrate Temperature Measurement during Ion Implantation

A quantitative estimation of the substrate temperature rise in situ during ion implantation is performed using a wide range infrared thermometer. The accuracy of the measurement is within ±3°C. The ion implantation is carried out on a silica glass wafer and the temperature rise is measured for He+, B+, N+, N+2, P+ and BF+2 ion species. The higher the implant power is, the higher becomes the substrate temperature, and an implant power of 6 W/cm2 raises the substrate temperature to 730°C. The mass dependence of the temperature rise is observed, and is explained by the electrical and nuclear stopping power of the substrate.

Hydrophobic Conversion of the Chemical-Vapor-Deposited SiO2 Surface

The surface silanol groups of SiO2 react with alcohols and other organic compounds to form alcoxyl groups in situ and their surfaces change into hyprophobic. These surface treatments were applied to the Chemical-Vapor-Deposited SiO2 films, which are widely used in semiconductor devices for passivation and insulation. The properties of the CVD-SiO2 surfaces treated with various alcohols, phenol and silane derivatives were investigated by measuring the contact angle against H2O. The alcoxyl groups were quantitatively evaluated by mass-spec-trometry. It was found that the properties of the treated surface depend on the structure and number of the alcoxyl groups formed, and that the hydrophobic natures of the CVD-SiO2 surfaces can be precisely controlled through these surface treatments.

A wideband low-noise analog delay line

A 128-bit color signal delay line for commercial TV, successfully operated by introducing a self-aligned electrode and an integrated low-noise analog sample holder to buried-channel charge-transfer devices, will be discussed.

A new spike noise elimination technique for photosensitive arrays

A linear photosensor array having a high S/N ratio (more than 35 dB) with excellent resolution capability has been developed, using a neighboring bit correlation principle technique.

A simple method for measuring the interface state density

A simple method for measuring interface state density distribution of an MIS capacitor is proposed. The method is the expanded one which is based on comparing a measured quasistatic C‐V curve to ideal characteristics. The measurement can be achieved semiautomatically and simultaneously with the quasistatic capacitance measurement by using analog systems. And rather time‐consuming computer calculation is not necessary. The completed apparatus can measure the interface state density in the range of 1010−3×1012/cm2· eV for standard Al–SiO2–Si capacitors. It is necessary for precise measurement to determine accurately the doping density of substrate and insulator capacitance.

A wide-band low-noise charge transfer video delay line

A new wide-band low-noise charge transfer video delay line is introduced utilizing a bulk charge transfer device (BCD) with a self-aligned electrode structure, and a simple integrated sample-hold circuit. Brief analysis of charge transfer characteristics of the BCD and design considerations for the proposed device are included. Several kinds of 128-element devices are designed and examined. Measured transferred signal bandwidth is 4 MHz at 10 MHz clock of voltage swing as low as 10 V, with signal-to-noise (S/N) ratio of 42 dB. The device itself can operate beyond 20 MHz clock rate. Moreover, the device features the use of an elaborate sample-hold circuit to eliminate the complex reset pulse and filtering circuitry, high packing density of 18 /spl mu/m per element with 3-/spl mu/m line spacings assuring a high fabrication yield, and process compatibility with conventional Si gate MOS technology.

Experimental Research of the All Solid-State Color TV Camere

最近, 固体撮像板の開発がさかんとなり, すでに100×100絵素程度のものが製品化されており, 多絵素化, 低価格化への努力が進あられつつある.固体撮像板は小形軽量で安定性のあるカラーテレビカメラを実現するには好適であるが, 撮像管とは異なった問題が生じてくる.筆者らは, これらの問題点を追求するため, 先に筆者らが試作した画像ファイル読出し用のMOS形固体撮像板3枚を用いてテレビカメラを試作し, 感度, S/N等の電気的特性や, レジストレーションの問題光学系の問題等につき検討を行った.