Yu-Lin Chao

Cooling performance of silicon-based thermoelectric device on high power LED

In this paper, a new thermal management application of silicon-based thermoelectric (TE) device on high power LED is unveiled. The silicon-based TE device is fabricated by the microfabrication and flip-chip assembly process. Thermal images photographed by infrared camera demonstrate the cooling function of the silicon-based TE devices. Because the LED chip is encapsulated in a package, the junction temperature of the LED chip cannot be measured directly. An electrical-thermal conversion method is used to measure the junction temperature of the high power LED. The result shows that the silicon-based thermoelectric device can effectively reduce the thermal resistance of the high power LED.

Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications

In this study, we used simulation technique to analyze the thermal behaviors and investigate the thermal issues of a designed system in package (SiP) for network system application that based on a three dimensional integrated circuit (3D IC) structure. The 3D IC SiP has an interposer which with regularly embedded through-silicon vias (TSVs); there are one CPU chip and two DRAM chips planted on the top side and bottom side of the interposer, respectively. The interposer with chips is bonded on a BT substrate; the BT substrate is bonded on a PCB; and a metallic heat spreader is placed on and glued to the CPU chips back-side. Because a 3D IC SiP with TSVs is so complicate for modeling and very difficult for meshing, this study attempted to use the equivalent models of embedded TSV, bump/solder bond and metallic trace to simplify a detail 3D IC model. We introduced a slice model, that four stacked chips on an interposer and each chip has two heaters and TSVs, to verify the accuracy and feasibility of the equivalent model by comparing to the detail model, the results of both models show that they are in a good agreement. By using the equivalent model to simulate the studied 3D IC integrated SiP; we found the CPU temperature would be dominated by the cooling capability of a thermal module that attached on the heat spreader. As for the DRAM chips that underneath the interposer, it is inevitable to have a quite high temperature due to the temperature superposition effect and an obstructed heat flow path. In fact, the severely high temperature of the chips under an interposer should be the main thermal issue for such a 3D IC SiP because there is no easy thermal solution for these chips.

Estimation for equivalent thermal conductivity of silicon-through vias TSVs used for 3D IC integration

In this study, thermal performance of 3D IC integration is investigated. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, a slice model to imitate a 3D memory stacked chip is adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.

IGBT power module packaging for EV applications

Insulated gate bipolar transistor (IGBT modules are widely used in power electronics applications such as vehicle and household applications as well as industry to realize energy savings with higher efficiency, smaller size, low cost, higher reliability and more environmental safety. However, due to the large power generation of IGBT and diode chips and harsh application environment of vehicle applications, reliability is an important issue. In this paper, the 600V, 450A IGBT high power module packaging technologies for electrical vehicle are developed and verified. The integrated optimum design of thermal, stress and electrical designs is established. Power module assembly technologies with high reliability include chip and DBC (direct bond copper) bonding with low void rate, heavy Al wire bonding and module encapsulation are developed. Finally, the performance of power module is verified by module testing and EV platform testing. The results show that the optimum design and assembly process can reduce junction temperature, thermal stress and parasitic effects of IGBT power modules. The power modules have good performance that can successfully pass through the module and EV platform tests.

Through-Silicon Hole Interposers for 3-D IC Integration

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs

In this study, a very low-cost silicon interposer with many through-silicon holes (TSHs) for 3D IC integration system-in-package (SiP) applications is proposed. Unlike TSVs (through-silicon vias), the uniqueness of this design is there is not the dielectric layer, barrier layer, seed layer, filled Cu, and thus CMP and TSV Cu reveal are not necessary for the TSHs. The vertical interconnects between (face-to-face) the top chips and bottom chips of the TSH interposer are through Cu wires or columns. The electrical, thermal and mechanical behaviors of this new design are demonstrated by nonlinear finite element simulations.

Low-cost TSH (through-silicon hole) interposers for 3D IC integration

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Design, fabrication, and calibration of stress sensors embedded in a TSV interposer in a 300mm wafer

In this study, the design, fabrication, and calibration of the piezoresistive stress sensors [1-18] embedded in a TSV (through silicon via) interposer in a 300mm wafer are investigated. The results presented herein should be useful for the development of 3D integration such as measuring the strength of the TSV device and interposer wafers, during and after all the processes such as wafer thinning, SiO2 deposition, metallization, and electroplating.

600V, 450A IGBT power module for 50kw electrical vehicle

Insulated gate bipolar transistor (IGBT) power modules are widely used in household, industry and vehicle applications due to the features of higher efficiency, smaller size, low cost and higher reliability. However, the large power dissipation of IGBT and diode chips and harsh application environment of vehicle, reliability is an important issue. In this paper, the 600V, 450A IGBT power module packaging technologies for 50kW electrical vehicle (EV) are developed and verified. The integrated electrical, thermal, and stress design is established. Module assembly technologies include chip on direct bond copper (DBC) substrate bonding, DBC substrate on base plate bonding, heavy Al wire bonding are developed. Finally, the performance of power module is verified by module testing, system platform testing and EV vehicle testing. The results show that the IGBT power modules have good performance and successfully pass through the system platform and EV vehicle tests.

Thermal Measurement and Simulation of 3D stacked die packages

3D packaging has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-in-package solution. 3D packages contain multiple heat sources that produce high power density. Heat dissipation has become a critical issue. However, unlike the single-chip package, for which thermal resistance can be easily defined and measured, the presence of multiple heat sources in multi-chip packages makes the definition of thermal resistance difficult. In addition, multiple chip temperature typically needs to be measured at various power level combinations. In this paper, the thermal performance of two dies stacked plastic ball grid array package (PBGA) has been studied. The junction-to-air thermal resistances are measured by thermal-test-chip method following the JEDEC standard environment. Thermal effects of different power level combination are discussed. In addition, the validity of the superposition technique was evaluated in the determination of junction temperatures with change in power of the various die. Finally, the thermal behavior of packages has been analyzed and validated by computational fluid dynamics (CFD) simulation.