Ming-Jui Yang

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.

Study of thermal stability of nickel monogermanide on single- and polycrystalline germanium substrates

We have investigated the thermal stability of nickel monogermanide (NiGe) films formed by rapid thermal annealing on both single- and polycrystalline Ge substrates. We found that the NiGe phase is the only one present after nickel germanidation in the temperature range 400–700°C. A fairly uniform NiGe film formed on the single-crystalline Ge; it possessed excellent resistivity (15.6μΩcm) and was thermally stable up to 550°C, but it degraded rapidly at higher temperatures as a result of agglomeration. In contrast, the NiGe film formed on the polycrystalline Ge exhibited much poorer thermal stability, possibly because of polycrystalline Ge grain growth, which resulted in columnar NiGe grains interlaced with Ge grains that had a dramatically increased sheet resistance. As a result, we observed that the sheet resistances of NiGe lines subjected to annealing at 500°C depended strongly on the linewidth when this width was comparable with the grain size of the polycrystalline Ge.

The characteristics of hole trapping in HfO2/SiO2 gate dielectrics with TiN gate electrode

The characteristics of charge trapping during constant voltage stress in an n-type metal–oxide–semiconductor capacitor with HfO2∕SiO2 gate stack and TiN gate electrode were studied. We found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross-section model. In particular, the flatband voltage shift (ΔVfb) is mainly caused by the trap filling instead of the trap creation [Zafar et al., J. Appl. Phys. 93, 9298 (2003)]. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode.

A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices

The erase and retention characteristics of MONOS, MANOS and BE-SONOS devices are examined in detail in order to determine their mechanisms. The erase transient current (J) is extracted and plotted against the tunnel oxide electric field (ETUN). Our results show that the erase speed ranking is BE-SONOS > MANOS > MONOS. The difference in erase speed comes from the different erase mechanisms of these devices. The retention characteristics are also compared and discussed.

Study of the Erase Mechanism of MANOS (

The erase characteristics and mechanism of metal- Al2O3-nitride-oxide-silicon (MANOS) devices are extensively studied. We use transient analysis to transform the erase curve (VFB - time) into a J-E curve (J = transient current, E = field in the tunnel oxide) in order to understand the underlying physics. The measured erase current of MANOS is three orders of magnitude higher than that can be theoretically provided by substrate hole current. In addition, the erase current is very sensitive to the Al2O3 processing condition - also inconsistent with substrate hole injection model. Thus, we propose that MANOS erase occurs through an electron detrapping mechanism. We have further carried out a refill test and its results support the detrapping model. Our results suggest that the interfacial layer between Al2O3 and nitride is a key process that dominates the erase mechanism of MANOS.

\hbox{Metal/Al}_{2}\hbox{O}_{3}/\hbox{SiN/SiO}_{2}/\hbox{Si}

Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with 390-nm-thick SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) ferroelectric film and 8-nm-thick hafnium oxide (HfO/sub 2/) layer on silicon substrate have been fabricated and characterized. It is demonstrated for the first time that the MFIS stack exhibits a large memory window of around 1.08 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 18% degradation in the memory window after 10/sup 9/ switching cycles. The excellent performance is attributed to the formation of well-crystallized SBT perovskite thin film on top of the HfO/sub 2/ buffer layer, as evidenced by the distinctive sharp peaks in X-ray diffraction (XRD) spectra. In addition to its relatively high /spl kappa/ value, HfO/sub 2/ also serves as a good seed layer for SBT crystallization, making the proposed Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure ideally suitable for low-voltage and high-performance ferroelectric memories.

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In this letter, high-performance p-channel polycrystalline-silicon thin-film transistors (TFTs) using hafnium- silicate (HfSiO_x) gate dielectric are demonstrated with low- temperature processing. Because of the higher gate-capacitance density, TFTs with HfSiO_x gate dielectric exhibit excellent device performance in terms of higher I_ON/I_OFF current ratio, lower subthreshold swing, and lower threshold voltage (V_th) albeit with slightly higher OFF-state current. More importantly, the mobility of TFTs with HfSiO_x gate dielectric is 1.7 times that of TFTs with conventional deposited-SiO₂ gate dielectric.

High-performance Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure for nondestructive readout memory

A bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005) using Al2O3 top blocking layer and metal gate (MA BE-SONOS) is proposed to provide very fast erase speed without erase saturation. Compared with MANOS (Shin et al., 2005) using a thick (4.5 nm) tunnel oxide, MA BE-SONOS shows dramatically faster erase speed, owing to the help of bandgap engineered ONO barrier that facilitates hole tunneling. Compared with BE-SONOS using P+-poly gate and top oxide, MA BE-SONOS does not show any erase saturation, owing to the help of metal gate and AI2O3 blocking layer, which greatly reduce gate injection during erase. Very large memory window (>7 V) can be achieved with excellent data retention. MA BE-SONOS overcomes the erase difficulty in SONOS-type devices, and is highly potential in the future flash memory technology.

High-Performance and Low-Temperature-Compatible p-Channel Polycrystalline-Silicon TFTs Using Hafnium-Silicate Gate Dielectric

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_x, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I_on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th), relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_x, as the gate dielectric had ca. 1.73 times the mobility (mu_FE) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_x, TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, mu_FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO_x, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.

MA BE-SONOS: A Bandgap Engineered SONOS using Metal Gate and Al2O3 Blocking Layer to Overcome Erase Saturation

The effects of tantalum (Ta) adhesion layer on the ferroelectric and microstructural properties of sol-gel-derived SrBi2Ta2O9 (SBT) films are reported in this study. Compared to the traditional titanium (Ti) adhesion layer, the Ta adhesion layer results in more favorable, highly (115) textural structure of SBT films and therefore higher polarization and dielectric constant. The remnant polarization value of the SBT films crystallized at 750 °C increases from 11.1 to 14.2 μC/cm2 at 5 V, and the dielectric constant increases from 175 to 225. The observed improvement in the electrical properties of SBT films is ascribed to the superior microstructure of Pt thin film on Ta, which has been characterized by x-ray diffraction spectrum (XRD). XRD patterns clearly indicate that the Ti adhesion layer favors c-axis crystalline structure that is undesirable for ferroelectric properties. Moreover, secondary ion mass spectrometer profiles strongly indicate that Ti atoms diffuse deeply into the bulk of SBT thin films af...