Koji Usuda

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

High performance strained-Si p-MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology

We have proposed a new MOSFET structure, strained-Si/Si/sub 0.9/Ge/sub 0.1/-on-Insulator (SSGOI) MOSFETs applicable to the sub-100 nm generation. This SSGOI structure was successfully fabricated by the combination of SIMOX technology and the Si re-growth technique. The strained-Si in SSGOI was found to have good crystal quality and very flat interfaces. SSGOI p-MOSFETs exhibited good FET characteristics. It was demonstrated, for the first time, that the hole mobility of the SSGOI p-MOSFETs is higher that of the universal mobility of conventional Si p-MOSFETs.

Device Design and Electron Transport Properties of Uniaxially Strained-SOI Tri-Gate nMOSFETs

We propose effective subband engineering for electron mobility enhancement on a (110) surface, utilizing uniaxial tensile strain along (110) direction. This strain causes the re-population of electrons from fourfold valleys to twofold valleys, resulting in high mobility enhancement along the (110) direction. Using this concept, a 2.0x mobility enhancement in uniaxially strained silicon-on-insulator (SOI) trigate nMOSFETs with (110) sidewall channels has been realized. Here, the uniaxial tensile strain is applied by using anisotropic strain relaxation of biaxiallv strained-SOI substrates. It is also found that (110) current (strain) direction is the best for strained trigate nMOSFETs, suggesting that optimum multigate CMOS structures with enhanced mobility of both electrons and holes can be realized on a conventional (001) wafer in the same (110) current flow direction for nMOSFETs and pMOSFETs.

High-Performance Uniaxially Strained SiGe-on-Insulator pMOSFETs Fabricated by Lateral-Strain-Relaxation Technique

Novel uniaxially strained SiGe-on-insulator (SGOI) pMOSFETs with Ge content of 20% have been successfully fabricated by utilizing lateral (uniaxial) strain-relaxation process on globally (biaxially) strained SGOI substrates. Drastic increase of drain current (80%) caused by the change of strain from biaxial to uniaxial and the mobility enhancement of about 100% against the control Si-on-insulator pMOSFETs are observed in SGOI pMOSFET. This high mobility enhancement is maintained in high vertical effective fields as well as in short-channel devices. As a result, significant ION enhancement of 80% is demonstrated in 40-nm gate-length uniaxially strained SGOI pMOSFET

Scanning tunneling microscopy observation of hydrogen‐terminated Si(111) surfaces at room temperature

Scanning tunneling microscopy has been applied to observe hydrogen‐terminated Si(111) surfaces at room temperature. A clear image was easily observed for a Si surface prepared by rinsing in pure water with very low dissolved oxygen after removal of native oxide by 1% HF solution dipping. A smooth surface in an atomic scale was exhibited in a 50×50 nm area. Completely triangular‐shaped holes were observed on the surface. The holes were surrounded by steps which were very likely directed toward 〈112〉. The treatment of the surface was remarkably stable even after a 3 h air exposure. Furthermore, nm size pits were found at the bottom part of the triangular‐shaped holes. The results imply that the nm size pits appeared to be due to microdefects and that the pits might be the origin of surface etching at the Si surface.

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g/sub m/ of n-MOSFET with 40-nm epitaxial Si for 0.10-/spl mu/m gate length was 630 mS/mm at V/sub d/-1.5 V, and the drain current was 0.77 mA//spl mu/m. This g/sub m/ value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFETs are useful for future high-speed ULSI devices.

EXAMINATION OF SI(100) SURFACES TREATED BY ULTRAPURE WATER WITH 5 PPB DISSOLVED OXYGEN CONCENTRATION

Si(100) surfaces treated by ultrapure water with 5 ppb dissolved oxygen concentration after dipping in HF solution were examined by attenuated total reflection (ATR)–Fourier‐transform infrared (FT‐IR) spectroscopy, transmittance FT‐IR, and reflection high energy electron diffraction (RHEED). FT‐IR spectra and RHEED patterns depended on the rinsing time in the ultrapure water. The (111) and (110) facets appeared after rinsing for a long period of time (20–45 h) in 5 ppb dissolved oxygen concentration ultrapure water. It was suggested that the surface morphology depended on not only pH value but also the amount of etching.

Tenth micron p-MOSFET's with ultra-thin epitaxial channel layer grown by ultra-high-vacuum CVD

We have, for the first time, demonstrated silicon MOSFETs with an ultra-thin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, so it is easily possible to adjust the threshold voltage of the p-MOSFETs even in the case of n-type polysilicon gates. It was confirmed that choosing an ultra-thin epitaxial layer-in the 10 nm range-leads to suppression of the short-channel effects in n-type polysilicon gate buried-channel MOSFETs, while maintaining an appropriate value of threshold voltage.<<ETX>>

High-performance poly-Ge short-channel metal–oxide–semiconductor field-effect transistors formed on SiO2 layer by flash lamp annealing

To realize a stackable complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) on interlayer dielectrics for three-dimensional (3D) large-scale-integration devices, we investigated poly-Ge thin films formed by flash lamp annealing. The process resulted in crystalline grains of micrometer-order size, and the Hall-effect mobility of holes was as high as 200 cm2 V−1 s−1. A depletion-type trigate poly-Ge channel pMOSFET with a gate length of 80 nm formed on a poly-Ge film exhibited a drive current of 280 µA/µm at a drain voltage of −1 V and a gate overdrive of −1 V. The operation of inversion-type short-channel trigate poly-Ge nMOSFETs was also demonstrated.