Yoshihiko Moriyama

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique

A strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors. The GOI layer was formed by thermal oxidation of a strained SiGe layer grown epitaxially on a silicon-on-insulator (SOI) wafer. In transmission electron microscopy measurements, the obtained GOI layer exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface. The rms of the surface roughness of the GOI layer was evaluated to be 0.4 nm by atomic force microscopy. The residual Si fraction in the GOI layer was estimated to be lower than the detection limit of Raman spectroscopy of 0.5% and also than the electron energy loss spectroscope measurements of 3%. It was found that the obtained GOI layer was compressively strained with a strain of 1.1%, which was estimated by the Raman spectroscopy. Judging from the observed crystal quality and the strain value, this technique is promising for fabrication of high-mobilit...

High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain

We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-on-insulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%/spl sim/40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO/sub 2/-Ge interface.

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

A new approach to form strained SiGe-on-insulator (SGOI) channel transistors, allowing fabrication of MOSFETs with very high Ge fraction in selected areas on a silicon-on-insulator substrate, is demonstrated. This method consists of epitaxial growth of an SiGe layer with a low Ge fraction and local oxidation processes. An obtained SGOI pMOSFET with a Ge fraction of 0.93 exhibits up to a tenfold enhancement in mobility. It is also found that MOSFETs having strained SGOI channels with thicknesses of less than 5 nm exhibit hole-mobility enhancement factors of over two. These results indicate that the local SGOI channels fabricated by the proposed technique are promising for implementation of high-mobility SiGe or Ge-channel MOSFETs in system-on-chip (SoC) devices.

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

[110]-surface strained-SOI CMOS devices

We have newly developed [110]-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on [110]-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on [110]-surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of [110]-surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of [110]-surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of [110]-surface strained-SOI MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the [110]-surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a [110]-surface Si. As a result, the [110]-surface strained-SOI technology with optimization of the current flow directions of n- and p-MOS is promising for realizing higher speed scaled CMOS.

Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process

Electrical properties of Ge-rich SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures fabricated by Ge condensation process have been studied. The SGOI and GOI structures for Ge composition, xGe, larger than 0.4 exhibit p-type conduction. The hole density is found to rapidly increase from 1016 to 1018 cm-3 with an increase in xGe during the Ge condensation and to decrease down to low-1017 cm-3 when xGe reaches unity. Analyses of scanning spreading resistance microscopy have directly revealed that the SGOI and GOI structures are highly conductive along the crosshatched slip bands formed during the condensation, meaning that the holes are induced along the slip bands in SGOI and GOI films. As a result, it is concluded that the hole induced during the Ge condensation is strongly associated with the slip band formation.

Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique

Formation process of Ge-on-insulator (GOI) layers by Ge condensation with very high purity of Ge is clarified in terms of diffusion behaviors of Si and Ge in a SiGe layer. It is shown that the diffusion behavior affects the Ge condensation process, and the purity of GOI layer can be determined by the relation between oxidation and diffusion of Si. Experimental results support a model of GOI formation that the selective oxidation of Si in SiGe continues until the formation of a GOI layer with the residual Si fraction of less than 0.01%. Based on this model, we quantitatively clarify the reason why GOI layers can reach very low residual Si fraction without oxidizing Ge by calculating the diffusion behavior of Si during the Ge condensation process. As a result, we have found that the thermal diffusion of Si is sufficiently fast so that the selective oxidation of Si can continue during the GOI formation process until the averaged residual Si fraction in the SGOI layer becomes lower than 0.03%, which is essent...

Strain analysis in ultrathin SiGe-on-insulator layers formed from strained Si-on-insulator substrates by Ge-condensation process

Ultrathin strained SiGe-on-insulator (sSGOI) layers were fabricated by Ge condensation, in which Si1−xGex layers on strained Si-on-insulator (sSOI) substrates were oxidized, and their strain and defects were investigated. With increasing the Ge fraction x, the compressive strain in the SGOI layers was found to linearly increase up to ∼2%. The linear strain dependence on x was offset by the preexisting tensile strain in the sSOI substrate compared to that of conventional SGOI layers formed on unstrained SOI substrates. As a result, pseudomorphic sSGOI layers were obtained on the sSOI substrate up to higher x (∼0.75) than on a SOI substrate.

(110)-surface strained-SOI CMOS devices with higher carrier mobility

In this paper, we have studied [110]-surface strained-SOI n- and p-MOSFETs with higher carrier mobility, according to the reduced interband/intervalley scattering and the smaller effective mass of carriers even in [110] strained-Si channel. The strained-Si channel has been formed on [110] relaxed-SGOI substrates, fabricated by the Ge condensation technique (25%) on a [110]-surface SOI substrate. It is demonstrated, for the first time, that the electron and the hole mobility enhancements of [110] strained-SOI devices amount to 23% and 50%, respectively, against to those of [110] unstrained-MOSFETs. Especially, the [110] hole mobility enhancement against the (100)-universal mobility amounts to 103%, which is much higher than that of [110] strained-SOIs (53%). Therefore, the unbalance between n- and p-channel current drivability can be reduced in [110] strained-SOI CMOS.