Mitsuru Takenaka

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Evidence of low interface trap density in GeO2∕Ge metal-oxide-semiconductor structures fabricated by thermal oxidation

We have fabricated GeO2∕Ge metal-oxide-semiconductor (MOS) structures by direct thermal oxidation of Ge substrates. The interface trap density (Dit) of Al∕GeO2∕Ge MOS structures, measured by the low temperature conductance method including the effect of the surface potential fluctuation, is found to be reduced as the oxidation temperature increases. The minimum values of Dit can be obtained for the oxidation around 575°C, which is in the maximum temperature range where GeO volatilization does not occur under atmospheric pressure of O2. It is also found that the hydrogen annealing before Al gate formation is effective for the passivation of GeO2∕Ge interface states. It is clarified, as a result, that the minimum Dit value lower than 1011cm−2eV−1 can be obtained for GeO2∕Ge MOS interfaces fabricated by direct oxidation of Ge substrates.

High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using

An ultrathin equivalent oxide thickness (EOT) HfO₂/Al₂O₃/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al₂O₃ layer between HfO₂ and Ge for suppressing HfO₂-GeO<i>x</i> intermixing, resulting in a low-interface-state-density (<i>D</i>_it) GeO<i>x</i>/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the <i>D</i>_it in 10¹¹ cm^-2·eV^-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm²/V·s and peak electron mobilities of 754 and 689 cm²/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO₂/Al₂O₃/GeO<i>x</i>/Ge gate stacks.

\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}

An electron cyclotron resonance (ECR) plasma postoxidation method has been employed for forming Al2O3/GeOx/Ge metal-oxide-semiconductor (MOS) structures. X-ray photoelectron spectroscopy and transmission electron microscope characterizations have revealed that a GeOx layer is formed beneath the Al2O3 capping layer by exposing the Al2O3/Ge structures to ECR oxygen plasma. The interface trap density (Dit) of Au/Al2O3/GeOx/Ge MOS capacitors is found to be significantly suppressed down to lower than 1011 cm−2 eV−1. Especially, a plasma postoxidation time of as short as 10 s is sufficient to reduce Dit with maintaining the equivalent oxide thickness (EOT). As a result, the minimum Dit values and EOT of 5×1010 cm−2 eV−1 and 1.67 nm, and 6×1010 cm−2 eV−1 and 1.83 nm have been realized for Al2O3/GeOx/Ge MOS structures with p- and n-type substrates, respectively.

Gate Stacks Fabricated by Plasma Postoxidation

An ultrathin equivalent oxide thickness (EOT) Al₂O₃/ GeO_x/Ge gate stack with a superior GeO_x/Ge metal-oxide-semiconductor (MOS) interface and p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) using this gate stack have been fabricated by a plasma post oxidation method. The properties of the GeO_x/ Ge MOS interfaces are systemically investigated, and it is revealed that there is a universal relationship between the interface state density (<i>D</i>_it) at the GeO<i>x</i>/Ge interface and the GeO_x interfacial layer thickness. Ge pMOSFETs on a (100) Ge substrate using the Al₂O₃/GeO_x/Ge gate stack have been demonstrated with an EOT down to 0.98 nm. It is found that the Ge pMOSFETs exhibit the peak hole mobility values of 515, 466, and 401 cm²/ V·s at an EOT of 1.18, 1.06, and 0.98 nm, respectively, which has much weaker EOT dependence than the trend of the hole mobility values reported so far, because of low <i>D</i>_it of the present gate stack in the ultrathin EOT region of ~1 nm.

Al2O3/GeOx/Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation

We have studied the impact of the Al2O3 inter-layer on interface properties of HfO2/InGaAs metal-oxide-semiconductor (MOS) interfaces. We have found that the insertion of the ultrathin Al2O3 inter-layer (2 cycle: 0.2 nm) can effectively improve the HfO2/InGaAs interface properties. The frequency dispersion and the stretch-out of C-V characteristics are improved, and the interface trap density (Dit) value is significantly decreased by the 2 cycle Al2O3 inter-layer. Finally, we have demonstrated the 1-nm-thick capacitance equivalent thickness in the HfO2/Al2O3/InGaAs MOS capacitors with good interface properties and low gate leakage of 2.4 × 10−2 A/cm2.

High-Mobility Ge pMOSFET With 1-nm EOT

All-optical flip-flop operation of multimode interference bistable laser diodes (MMI-BLDs) was experimentally demonstrated for the first time. The MMI-BLD was prepared with a conventional ridge waveguide laser diode fabrication procedure, suitable for photonic integrated circuits. Bistable switching via two-mode bistability was obtained with approximately 0-dBm input powers due to cross-gain saturation and the saturable absorbers. Bit-length conversion was successfully obtained with noninverted and inverted outputs. This device will be useful in future photonic systems requiring all-optical latching functions such as optical memory, self-routing, and further optical signal processing.

\hbox{Al}_{2} \hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}

We reveal that the MOVPE-based gas-phase doping can yield lower arsenic diffusion constant and lower leakage current n⁺/p junctions in Ge compared with conventional ion-implantation doping. Thus, the gas-phase doping is quite effective for realizing high-performance Ge n-channel MOSFETs. By using gas-phase doping for source/drain junction formation, the (100) GeO₂/Ge nMOSFETs have achieved high electron mobility of 1020 cm²/V·s while maintaining low junction leakage current and high I_on/I_off ratio of 10⁵. Furthermore, the (110) GeO₂/Ge nMOSFETs have also shown high electron mobility and high I_on/I_off ratio.

Gate Stack Fabricated by Plasma Post Oxidation

We have fabricated GeO2/Ge interfaces on (100), (110), and (111) orientation substrates by direct thermal oxidation. The x-ray photoelectron spectroscopy analyses suggest that the Ge oxides are composed of GeO2 and have almost the same interfacial structure, independent of the surface orientations. The gate current conduction mechanism through the GeO2/Ge metal-oxide-semiconductor structure is dominated by Fowler–Nordheim tunneling. In addition, the barrier height between Ge and GeO2 is evaluated to be 1.2–1.4 eV. In interface trap density (Dit) measurement by using the low temperature conductance method, the amount of Dit in the conduction band side is also almost the same, while Dit in the valence band side is lowest for the (111) surface. Minimum detectable Dit is lower than 1×1011 eV−1 cm2 for all the orientations. These surface orientation dependences of the GeO2/Ge interface properties are quite different from those of the SiO2/Si interface.

1-nm-capacitance-equivalent-thickness HfO2/Al2O3/InGaAs metal-oxide-semiconductor structure with low interface trap density and low gate leakage current density

We have demonstrated thin body III–V-semiconductor-on-insulator (III-V-OI) n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) on a Si wafer fabricated using a novel direct wafer bonding (DWB) process. A 100-nm-thick InGaAs channel was successfully transferred by the low damage and low temperature DWB process using low energy electron cyclotron resonance (ECR) plasma. The transferred InGaAs-OI nMOSFET on the Si wafer exhibited a high electron channel mobility of 1200 cm2V-1s-1, indicating that the present DWB process allows us to form thin III-V-OI channels without serious plasma and bonding damage. This technology is expected to open up the possibility of integrating the ultrathin body III-V-OI MOSFETs on Si platform.