Mohammad Najmzadeh

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

In this paper, we report for the first time making multi-gate buckled self-aligned dual Si nanowires including two sub-100 nm cross-sectional cores on bulk Si substrate using optical lithography, hard mask/spacer technology, and local oxidation. ≈0.8 GPa uniaxial tensile stress was measured on the buckled dual nanowires using micro-Raman spectroscopy. The buckled multigate dual Si nanowires show excellent electrical characteristics, e.g., 62 mV/decade and 42% low-field electron mobility enhancement due to uniaxial tensile stress in comparison to the non-strained device, all at VDS = 50 mV and 293 K.

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 × 1019, 5 × 1018, and 1 × 1018 cm-3 were used for quasi-stationary device simulations of JL and AM MOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO2 gate oxide thickness (VDS = 0 V; T = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, Ntacc/(CWeff), in strong accumulation regime.

Mobility extraction assessment in GAA Si NW JL FETs with cross-section down to 5 nm

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first step, addressing bias-dependency of various key MOSFET parameters (e.g. series resistance, channel width and gate-channel capacitance), non-uniform electron density due to corners and quantization. A significant bias-dependent series resistance variation in JL MOSFETs is reported above flat-band, leading to a significant mobility extraction accuracy drop of ~50%. All quasistationary device simulations were done on 100 nm long channel devices with 5-20 nm NW width, 2 nm SiO2 gate oxide thickness and 1×1019 cm-3 n-type channel doping using a constant mobility model (100 cm2/V·s).

Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling

Multi-gate architectures such as gate-all-around (GAA) Si nanowires are the promising candidates for aggressive CMOS downscaling due to the immunity to the issues regarding short channel effect, improved subthreshold slope and optimized power consumption. On the other hand, Si nanowires represent excellent mechanical properties e.g. yield strength of 10±2% [1] in comparison to 3.7% for bulk Si [2], a strong motivation to be used as interesting exclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels [3]–[5] or local band-gap modulation using >4 GPa uniaxial tensile stress in suspended Si channels to enhance band-to-band tunneling current in multi-gate Tunnel-FETs [6], all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels.

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

In this work we report an experimental study on accumulation-mode (AM) gate-all-around (GAA) nMOSFETs based on silicon nanowires with uniaxial tensile strain. Their electrical characteristics are studied from room temperature up to ∼400 K and carrier mobility, flat-band and threshold voltages are extracted and investigated.

Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs

We report for the first time the optimization of the channel lateral strain profile as a new technological booster for improved performance of multi-gate n-channel MOSFET. We find that quasi-uniform or flat-Gaussian-close-to-the-drain profiles are optimum for the Ion boosting of sub-50nm scaled MOSFETs, while the penalty on Ioff and subthreshold slope is minimum. The reported predictions use realistic lateral uniaxial strain profiles, with peaks up to few GPas and average values of hundreds of MPas.