Moon Han Park

An optimized densification of the filled oxide for quarter micron shallow trench isolation (STI)

Densification methods using H/sub 2/O and N/sub 2/ ambient annealing of the filled CVD oxide for quarter micron STI are compared. Although the H/sub 2/O ambient oxidation is more effective in terms of the resistance against the HF etching, volume expansion by the trench sidewall oxidation generates a large amount of stress in the narrow isolation region. However, an N/sub 2/ gas ambient annealing at high temperature shows a low stress and a low HF etch rate which enable us to fabricate the stable quarter micron STI.

Correlation between gate oxide reliability and the profile of the trench top corner in Shallow Trench Isolation (STI)

In order to develop a Shallow Trench Isolation (STI) which does not have trench corner induced degradation of the gate oxide, its integrities were evaluated with rounded, non-rounded top corner, and an addition of CVD SiO/sub 2/ spacer. In the experiment, we found that the rounded and SiO/sub 2/ spacered STI showed the best result meaning no harmful influence of the corner to the gate oxide integrity. Also, etch-back processes of the filled CVD SiO/sub 2/ were modified to eliminate the degradation of the gate oxide by a stress concentration at top corner kinks.

The Effect of Stress on Solid-Phase Epitaxial Regrowth in As+-Implanted Two-Dimensional Amorphized Si

The effect of stress induced by a chemical-vapor-deposited (CVD) SiO2 film on the solid-phase epitaxial (SPE) regrowth in As+-implanted, two-dimensional amorphized Si has been studied. Trench structures were used to form the two-dimensional amorphous layer and to induce the stress in the Si substrate. As+ implantation at an energy of 80 keV with a dose of 3×1015/cm2 amorphized the silicon surface and produced a curved amorphous/crystalline (a/c) interface under the bottom corner of the trenches. At the trenches filled with the high-tensile-stress CVD SiO2 film, the regrowth of the amorphous Si layers was retarded and a notch remained in the a/c interface immediately under the bottom corner of the trench after annealing at 500°C for 4 h. The regrowth retardation and the remaining notch were explained by the effect of the stress induced by the CVD SiO2 film on the activation barrier of the SPE regrowth.

A Novel T-Shaped Shallow Trench Isolation Technology

This paper describes a novel T-shaped shallow trench isolation (STI) technology, which has the same effective isolation length with conventional STI but significantly reduced aspect ratio. The T-shaped STI is formed using 2-step trench etches. After the formation of the 1st trench of a relatively low aspect ratio, oxide spacer is formed inside the trench sidewall. And the 2nd trench is made to ensure an effective isolation length. When T-shaped STI is filled with undoped silicate glass (USG) and high density plasma (HDP) oxide, the mouth of 2nd trench is closed by the overhang of filling materials so that the effective aspect ratio of T-shaped STI can be lowered. We evaluated the electrical characteristics of T-shaped STI. Also, we performed simulation of the stress distribution and the junction profile. T-shaped STI has shown comparable characteristics to conventional STI and no electrical or physical degradation was found. We have adopted this technology to 512 Mbit flash memory (0.5 µm cell pitch) and obtained excellent structural and electrical properties. In addition, we obtained the excellent gap filling ability even for the 1 Gbit flash memory (0.34 µm cell pitch) and beyond.

Effective reduction of threshold voltage variability and standby leakage using advanced co-implantation and laser anneal for low power applications

We have successfully reduced threshold voltage variation by combination of co-implantation and laser spike anneal on 45 nm low power SoC platform with conventional poly-Si/SiON gate stack. Doping profiles of CMOSFET channel is modulated through co-implantation of diffusion suppressor. We have explored the possibility of cluster carbon doping in order to minimize junction leakage degradation. Systematic junction profile design for n- and pFET enables us to reduce random dopant variation significantly without compromising standby leakage, drive current and gate oxide integrity, which finally contributes to RO ~5% performance improvement at equivalent Iddq and ensures high yield of SRAM array by reducing beta and gamma ratio variation.