Motoi Ashida

Performance and reliability improvements in poly-Si TFT's by fluorine implantation into gate poly-Si

High-performance and high-reliability TFTs have been obtained using a fluorine ion implantation technique. The fluorine implantation into the gate poly-Si of TFT caused a positive Vth shift, increased the ON current, and decreased the leakage current significantly. Our investigation indicates that the Vth shift originates from negative charges generated in the gate oxide by the fluorine implantation. The improvement of drain current is attributed to fluorine passivation of trap states in the poly-Si and to a modulation of offset potential due to the same negative charges under the offset region. Furthermore, high immunity against the -BT stress and TDDB of the gate oxide was achieved by the fluorine implantation. It is considered that the strong Si-F bonds created by the fluorine implantation raise the stress immunity. >

A 21-mW 4-Mb CMOS SRAM for battery operation

The authors describe a 21-mW 4-mB CMOS SRAM for the application of memory systems which operate on 3-V batteries. A low active power is achieved by novel circuit technologies. A thin-film transistor (TFT) load memory cell effectively reduces standby current to 0.4 mu A. A new multibit test circuit, which permits measurement of access time, is also introduced for a reduction of the test time. The authors describe the characteristics of the TFT memory cell and the improved memory cell design for stable cell operation. The 0.6- mu m process technology used to fabricate the 4-Mb SRAM and the chip performance are outlined. >

An analytical method of evaluating variation of the threshold voltage shift caused by the negative-bias temperature stress in poly-Si TFTs

The variation of the threshold voltage shift (V/sub th/ shift) caused by negative-bias temperature stress (-BT stress) in poly-crystalline silicon thin-film transistors (poly-Si TFTs) was investigated. Based on the chemical reaction caused by -BT stress at the poly-Si/SiO/sub 2/ interface and the poly-Si grain boundary, an analytical method of evaluating the variation of both the V/sub th/ shift and the initial V/sub th/ was proposed. It was shown from this analysis that the enlargement of the poly-Si grain, using Si/sub 2/H/sub 6/ gas could be a solution for efficient reduction of the easily hydrogenated dangling bonds which resulted in the V/sub th/ shift and suppression of the V/sub th/ shift and its variation. Moreover, it was suggested that there are two kinds of the dangling bonds; one is hydrogenated by hydrogenation and can be dehydrogenated by -BT stress; the other is not hydrogenated and the variation of its density is much smaller than the former.

An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-/spl mu/m design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT.