Mujahid Muhammad

Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBMs 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.

ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-/spl mu/m CMOS technology

Historically, the failure mode of the nMOS/lateral n-p-n (L/sub npn/) bipolar junction transistor (BJT) due to electrostatic discharge (ESD) is source-to-drain filamentation, as the temperature exceeds the melting temperature of silicon. However, as the gate-oxide thickness shrinks, the ESD failure changes over to oxide breakdown. In this paper, transmission line pulse (TLP) testing is combined with measurements of various leakage currents and numerical simulations of the electric field to examine the failure mode of an advanced 0.1-/spl mu/m CMOS technology, which is shown to be through gate-oxide breakdown. It is also shown by I/sub D/-V/sub G/ and I/sub G/-V/sub G/ measurements that the application of nondestructive ESD pulses causes gradual degradation of the oxide well before failure is reached, under the (leakage current) failure criteria used. Finally, the latent effects of stress-induced oxide degradation on the failure current I/sub f/ of the nMOS/L/sub npn/ are studied, and it is shown that as the device ages from an oxide perspective, its ESD protection capabilities decrease.

Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond

The on-resistance and failure current of electrostatic discharge (ESD) protection diodes in 90 nm and 65 nm bulk CMOS technologies is determined largely by the resistance and failure of metal lines, contacts or vias. With design optimization, P/sup +//N-well ESD diodes fabricated in a 90 nm bulk CMOS technology achieved a forward voltage drop of 1.66 V at 2 A, an on-resistance of 0.27 /spl Omega/ and a 100 ns TLP failure current greater than 5 A with a junction capacitance of only 125 fF, area of 330 /spl mu/m/sup 2/ and anode perimeter of 300 /spl mu/m.

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

In this work, the effect of design parameters on the internal and external latchup robustness of dual well (DW) and triple well (TW) test structures designed in 65nm bulk CMOS technology is studied. It is found that while both DW and TW latchup structures were robust for a positive-mode external latchup (latchup trigger current, ITRIG > 200mA), TW latchup structures were more susceptible to negative mode external latchup. The ITRIG for the worst case TW latchup structure was ~50% lower compared to a similarly designed test structure in DW. Isolation of injection sources is more efficient in TW as compared to DW design and can be further improved by appropriate design of I/O devices and guard rings surrounding the I/Os

Characterization and investigation of the interaction between hot electron and electrostatic discharge stresses using NMOS devices in 0.13 /spl mu/m CMOS technology

In this paper, the high-current characteristics encountered during electrostatic discharge (ESD) events using NMOS/Lnpn protection devices in a 0.13 /spl mu/m CMOS technology are investigated for different device parameters. The effects of silicide blocking and hot electron (HE) shifts on the second breakdown current of the NMOS devices are studied. The impact of nondestructive ESD stressing on HE shifts is also studied for both silicided and nonsilicided devices.

NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-/spl mu/m CMOS technology

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L/sub npn/ protection devices in a 0.13-/spl mu/m CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 /spl mu/m) devices fail because of source/drain filamentation, whereas longer (0.3 /spl mu/m) devices with thin (22 /spl Aring/) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I/sub t2/. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device.

Optical and electrical testing of latchup in I/O interface circuits

Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] test chip, which was designed in a flip-chip package. Case studies of several Inputs/Outputs (I/Os) are shown along with conclusions regarding layout and floorplanning to ensure the robustness to various types of latchup trigger events.

Failure Analysis of I/O with ESD Protection Devices in Advanced CMOS Technologies

Many types of ESD protection devices such as diodes, NFETs, SCRs and RC-triggered power clamps having different failure mechanisms are used in advanced CMOS technologies. Circuit schematic analysis and SEM failure analysis are utilized to clearly predict and identify the failing I/O driver/receiver devices and/or the various ESD protection devices during an ESD event.

Design automation to suppress cable discharge event (CDE) induced latchup in 90nm CMOS ASICs

Design automation tools have been developed to suppress CDE-induced latchup in CMOS ASICs. The tools govern the placement of I/Os and cores subject to CDE and automate the insertion of well and substrate contacts with varying periodicities around CDE susceptible cells according to rules derived from an analytical latchup model.

Electrostatic discharge induced oxide breakdown characterization in a 0.1 /spl mu/m CMOS technology

Historically, the failure mode of the NMOS/lateral NPN (Lnpn) due to electrostatic discharge (ESD) is source-to-drain filamentation as the temperature exceeds the melting temperature of silicon. However, as the oxide thickness shrinks, the ESD failure is instead due to oxide breakdown. In this paper, transmission line pulse (TLP) testing of the NMOS/Lnpn device is used to characterize the failure mode for a 0.1 /spl mu/m NMOS. The channel length and non-silicided source contact-to-gate spacing (SCG) are the main parameters in determining ESD protection capability. Using Id-Vg measurements, we show how oxide degradation before failure is detected with the leakage current failure criteria used. The latent effects of oxide degradation on the second breakdown current (It2) of the NMOS/Lnpn are identified. As the ultra-thin oxide (15 A) device ages from an oxide perspective, its ESD protection capabilities decrease.