Souvick Mitra

Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies

S-parameter test structures show total capacitances per perimeter of ESD diodes increased from ~0.42fF/mum in 90nm technologies to ~0.7fF/mum in 65nm and 45nm technologies. To achieve lower capacitances for high frequency circuits, layout and process optimization are needed. SCR devices from a 45nm technology show ~0.32fF/mum and can be used for circuit applications with stringent capacitance requirement. Two different BEOL wiring schemes are investigated for optimized metal coupling capacitance.

Evaluation of ESD characteristics for 65 nm SOI technology

With aggressive scaling and continuous drive for higher performance requirements, electrostatic discharge is becoming a major reliability challenge for advanced integrated circuits. Products must be designed with proper ESD protection circuits to provide adequate robustness and as the limits of the device capability are reached, factors like device reliability due to ESD sensitivity became more critical. In this paper, the ESD characteristics of I/O elements in 65nm SOI technology are thoroughly evaluated. With an appropriate design implementation using these discrete elements, industry standard ESD robustness can be achieved.

I/O Architecture For Improved ESD Protection In Deep Sub-Micron SOI Technologies

In this paper, the I/O structure described is based on a state of the art 65nm SOI technology designed for SRAM and logic applications (Leobandung et al, 2005). It is a twin-well partially depleted SOI (PDSOI) CMOS technology with gate oxide thicknesses of 1.05nm (SG) and 2.35nm (DG)

Degradation of High-

The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32-nm bulk CMOS technology was studied using I- V characteristics and charge pumping measurements. The impact of stress on drain saturation current (Idsat), threshold voltage (Vt), transconductance peak (gm), and subthreshold swing (SS) is reported. For ESD stress applied on the drain, little degradation was observed until the device failed by drain-to-source filamentation. In contrast, for stress applied on the gate, positive ESD-like stress decreases Idsat and increases Vt of the nMOSFETs significantly, and the degradation increases with the effective gate oxide thickness. Different from positive bias temperature instability (PBTI) stress, the Vt shift depends on temperature rather weakly, which indicates a new dominant charge-trapping mechanism on the time scale of ESD events. In addition to the degradation of Vt and Idsat, the positive stress also caused significant damage to the Si/oxide interface in the nMOSFETs with thick gate oxide. The degradation of Idsat, Vt , gm, and SS under positive stress is more severe for devices with high-k gate compared to devices with SiON gate. It is also shown that the degradation induced by negative ESD-like stress applied on the gate is much smaller compared to positive stress. Finally, the impacts of the stress on the gate leakage current and on the the subsequent PBTI degradation kinetics are also studied.

k

Catastrophic gate oxide breakdown of MOSFETs with high-k gate was characterized under ESD-like pulsed stress. It was found that the excessive gate current after gate oxide failure may result in a loss of gate contact and form a resistive path between the drain and source. Using constant voltage stress (CVS) method, the gate oxide breakdown voltages (VBD) of NMSOFETs and PMOSFETs were extracted. NMOSFETs under positive stress were found to have the smallest VBD, while the VBD of the PMOSFETs under positive stress were significantly increased due to the well resistance. Compared to that measured using the CVS method, the VBD from the transmission line pulse method (TLP) was smaller by only less than 10%. Despite the cumulative damages caused by the TLP method, the result is a conservative estimation of the breakdown voltage. The VBD corresponding to the failure time of 1-ns measured using TLP method agrees well with the extrapolation result from the CVS measurements on the time scale ranging from ∼100 ns to ∼20 µs, suggesting that the failure mechanism remains the same as in the longer time scale.

/Metal Gate nMOSFETs Under ESD-Like Stress in a 32-nm Technology

It is crucial to minimize the parasitic capacitance at a high-frequency I/O, found in applications such as high-speed serial links and radio receivers. Here, we study the bias-dependent capacitance of a poly-defined SOI diode-a popular ESD protection device according to C. Putnam et al. (2004), C. Entringer et al. (2005), M. Khazbinisky et al. (2005), S. Mitra et al. (2005), and S. Voidman et al. (1996). Also, we present a model for this diode; the model is intended for circuit simulation

Characterization of high-k/metal gate stack breakdown in the time scale of ESD events

A Design of Experiments (DOEs) matrix was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Based on measured samples, functionality test and leakage test show circuit performance degradation and larger fail rate after chip bonding on designs without ESD protection.

SOI Poly-defined Diode for ESD Protection in High Speed I/Os

Body contacted (BC) core logic/high speed (HS) and input/output (I/O) SOI PMOSFETs from 65 nm technology are shown to have higher degradation than the counterpart floating body (FB) devices under NBTI stress. It is also observed that concurrent HCI-NBTI (hot-carrier injection-negative bias temperature instability) leads to worst case degradation for the I/O and HS SOI p-channel MOSFETs. I/O PMOS devices stressed under HCI conditions at room temperature show NBTI-like behavior at higher stress voltages and combined HCI-NBTI behavior at lower stress voltages. HS PMOS devices stressed under HCI conditions show a combined HCI and NBTI degradation behavior across the entire stress bias range. Both HS and I/O devices degrade more when HCI stressed with FB at high stress voltages; however the degradation becomes comparable to BC devices at lower stress voltages.