Kiran V. Chatty

Reliability aspects of gate oxide under ESD pulse stress

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBMs 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.

Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies

We explore the effect of layout factors on the turn-on time of silicon controlled rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a very fast transmission line pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90nm CMOS ASICs

We report the characterization of diode and bipolar triggered SCRs with VFTLP measurements and product ESD testing. A dual base Darlington bipolar triggered SCR (DbtSCR) in a triple well structure is demonstrated to provide 4 KV HBM, 300 V MM and 1000 V CDM protection for 90 nm ASIC I/Os. A very fast turn-on time of 460 ps was measured for the DbtSCR, compared to 8 ns for a diode triggered SCR.

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the silicide-blocked drain/source and the polysilicon gate is avoided. For 2.5V thick oxide devices, drain-to-substrate junction shorting was observed, whereas, for 1.0V thin oxide devices, gate-oxide breakdown failure occurred

Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond

The on-resistance and failure current of electrostatic discharge (ESD) protection diodes in 90 nm and 65 nm bulk CMOS technologies is determined largely by the resistance and failure of metal lines, contacts or vias. With design optimization, P/sup +//N-well ESD diodes fabricated in a 90 nm bulk CMOS technology achieved a forward voltage drop of 1.66 V at 2 A, an on-resistance of 0.27 /spl Omega/ and a 100 ns TLP failure current greater than 5 A with a junction capacitance of only 125 fF, area of 330 /spl mu/m/sup 2/ and anode perimeter of 300 /spl mu/m.

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

In this work, the effect of design parameters on the internal and external latchup robustness of dual well (DW) and triple well (TW) test structures designed in 65nm bulk CMOS technology is studied. It is found that while both DW and TW latchup structures were robust for a positive-mode external latchup (latchup trigger current, ITRIG > 200mA), TW latchup structures were more susceptible to negative mode external latchup. The ITRIG for the worst case TW latchup structure was ~50% lower compared to a similarly designed test structure in DW. Isolation of injection sources is more efficient in TW as compared to DW design and can be further improved by appropriate design of I/O devices and guard rings surrounding the I/Os

Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies

S-parameter test structures show total capacitances per perimeter of ESD diodes increased from ~0.42fF/mum in 90nm technologies to ~0.7fF/mum in 65nm and 45nm technologies. To achieve lower capacitances for high frequency circuits, layout and process optimization are needed. SCR devices from a 45nm technology show ~0.32fF/mum and can be used for circuit applications with stringent capacitance requirement. Two different BEOL wiring schemes are investigated for optimized metal coupling capacitance.

Process and design optimization of a protection scheme based on NMOSFETs with ESD implant in 65nm and 45nm CMOS technologies

Process and design optimization of NMOSFETs with ESD implant is presented. A 2 V reduction in trigger voltage, a 30% higher failure current, 50% reduction in on-resistance is achieved with a 13X increase in leakage current for a 2.5 V NMOSFET. Self-protected NMOSFETs with ESD implant enables 40% or larger decrease in NMOSFET area for a non-mixed voltage and mixed voltage I/O.

Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.