Rahul Mishra

Degradation of High-

The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32-nm bulk CMOS technology was studied using I- V characteristics and charge pumping measurements. The impact of stress on drain saturation current (Idsat), threshold voltage (Vt), transconductance peak (gm), and subthreshold swing (SS) is reported. For ESD stress applied on the drain, little degradation was observed until the device failed by drain-to-source filamentation. In contrast, for stress applied on the gate, positive ESD-like stress decreases Idsat and increases Vt of the nMOSFETs significantly, and the degradation increases with the effective gate oxide thickness. Different from positive bias temperature instability (PBTI) stress, the Vt shift depends on temperature rather weakly, which indicates a new dominant charge-trapping mechanism on the time scale of ESD events. In addition to the degradation of Vt and Idsat, the positive stress also caused significant damage to the Si/oxide interface in the nMOSFETs with thick gate oxide. The degradation of Idsat, Vt , gm, and SS under positive stress is more severe for devices with high-k gate compared to devices with SiON gate. It is also shown that the degradation induced by negative ESD-like stress applied on the gate is much smaller compared to positive stress. Finally, the impacts of the stress on the gate leakage current and on the the subsequent PBTI degradation kinetics are also studied.

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Catastrophic gate oxide breakdown of MOSFETs with high-k gate was characterized under ESD-like pulsed stress. It was found that the excessive gate current after gate oxide failure may result in a loss of gate contact and form a resistive path between the drain and source. Using constant voltage stress (CVS) method, the gate oxide breakdown voltages (VBD) of NMSOFETs and PMOSFETs were extracted. NMOSFETs under positive stress were found to have the smallest VBD, while the VBD of the PMOSFETs under positive stress were significantly increased due to the well resistance. Compared to that measured using the CVS method, the VBD from the transmission line pulse method (TLP) was smaller by only less than 10%. Despite the cumulative damages caused by the TLP method, the result is a conservative estimation of the breakdown voltage. The VBD corresponding to the failure time of 1-ns measured using TLP method agrees well with the extrapolation result from the CVS measurements on the time scale ranging from ∼100 ns to ∼20 µs, suggesting that the failure mechanism remains the same as in the longer time scale.

/Metal Gate nMOSFETs Under ESD-Like Stress in a 32-nm Technology

We present the development of ESD lateral NPN device in 14nm FinFET SOI CMOS technology using body-contact and floating-body approaches. The effects of key design factors including base length, base doping, body resistance on the triggering and ESD performance of LNPN device are investigated to achieve an optimized design.

Characterization of high-k/metal gate stack breakdown in the time scale of ESD events

An ESD TCAD Workbench with a library of ESD and Latchup devices and circuits has been developed in a 32 nm bulk CMOS technology. The devices which were developed from process and layout information were calibrated to experimental results in the low current DC and high-current/high-temperature ESD regime. The failure currents of ESD devices correlated to the experimental data to within 15% and the failure location of the devices in TCAD were confirmed using failure analysis.

Design and optimization of ESD lateral NPN device in 14nm FinFET SOI CMOS technology

Body contacted (BC) core logic/high speed (HS) and input/output (I/O) SOI PMOSFETs from 65 nm technology are shown to have higher degradation than the counterpart floating body (FB) devices under NBTI stress. It is also observed that concurrent HCI-NBTI (hot-carrier injection-negative bias temperature instability) leads to worst case degradation for the I/O and HS SOI p-channel MOSFETs. I/O PMOS devices stressed under HCI conditions at room temperature show NBTI-like behavior at higher stress voltages and combined HCI-NBTI behavior at lower stress voltages. HS PMOS devices stressed under HCI conditions show a combined HCI and NBTI degradation behavior across the entire stress bias range. Both HS and I/O devices degrade more when HCI stressed with FB at high stress voltages; however the degradation becomes comparable to BC devices at lower stress voltages.

Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology

In this review, the following reliability concerns: hot carrier reliability, negative-bias temperature instability (NBTI), time depended dielectric breakdown (TDDB) and electrostatic discharge, are discussed individually, and recognizing that the responsible mechanisms quite often are active simultaneously, their interdependence and interaction is also discussed