N. Srirattana

Reconfigurable RFICs in Si-based technologies for a compact intelligent RF front-end

This paper presents reconfigurable RF integrated circuits (ICs) for a compact implementation of an intelligent RF front-end for multiband and multistandard applications. Reconfigurability has been addressed at each level starting from the basic elements to the RF blocks and the overall front-end architecture. An active resistor tunable from 400 to 1600 /spl Omega/ up to 10 GHz has been designed and an equivalent model has been extracted. A fully tunable active inductor using a tunable feedback resistor has been proposed that provides inductances between 0.1-15 nH with Q>50 in the C-band. To demonstrate reconfigurability at the block level, voltage-controlled oscillators with very wide tuning ranges have been implemented in the C-band using the proposed active inductor, as well as using a switched-spiral resonator with capacitive tuning. The ICs have been implemented using 0.18-/spl mu/m Si-CMOS and 0.18-/spl mu/m SiGe-BiCMOS technologies.

Reconfigurable RFICs for frequency-agile VCOs in Si-based technology for multi-standard applications

This paper presents novel reconfigurable RFICs for intelligent radio applications. It includes a new fully tunable active inductor (TAI) along with frequency-agile VCOs. The ICs are implemented on both 0.18 /spl mu/m Si-CMOS and 0.18 /spl mu/m SiGe-BiCMOS technologies. The novelty of the TAI lies in the use of a tunable active feedback resistor that results in inductances tunable from 0.1 nH to 15 nH with Q < 50 in C-band. Very wideband reconfigurable VCOs have been implemented using the proposed active inductor, and also with a switched-spiral topology. The VCO tuning ranges are as high as 4 GHz in the C-band. Analysis of the results, taking into account the technologies as well as the circuit topologies, is also presented.

Modeling and design techniques for RF power amplifiers

Achieve higher levels of performance, integration, compactness, and cost-effectiveness in the design and modeling of radio-frequency (RF) power amplifiers RF power amplifiers are important components of any wireless transmitter, but are often the limiting factors in achieving better performance and lower cost in a wireless communication system—presenting the RF IC design community with many challenges. The next-generation technological advances presented in this book are the result of cutting-edge research in the area of large-signal device modeling and RF power amplifier design at the Georgia Institute of Technology, and have the potential to significantly address issues of performance and cost-effectiveness in this area.

A high-efficiency multistage Doherty power amplifier for WCDMA

A comprehensive analysis of multistage Doherty amplifier, which can be used to achieve higher efficiency at great back-off compared to the classical Doherty amplifier, is presented. A novel set of design equations for a generalized N-stage Doherty amplifier is introduced. For the first time, this technique is applied to the design of a WCDMA power amplifier (PA). The designed PA meets WCDMA requirements, and exhibit a power-added efficiency (PAE) of 34.5% at 6 dB back-off and 16.9% at 12 dB back-off. These PAEs are 2 times and 4 times better, respectively, than that of a single stage linear PA at the same back-off levels. The PA is capable of delivering up to 28.6 dBm of output power, and has a maximum adjacent channel power leakage ratio of -38 dBc and -51 DBc at 5 and 10 MHz offset, respectively. To the best of the authors knowledge, these represent the best reported results of a Doherty amplifier for WCDMA application in the 1.95 GHz band, to date.

Linear RF CMOS power amplifier with improved efficiency and linearity in wide power levels

We demonstrate for the first time that both linearity and efficiency can be optimized for CMOS power amplifiers in the gigahertz range. A technique using large and small transistors in parallel at the output stage for efficiency and linearity enhancement is proposed. A small transistor is used for low power amplification where a larger transistor is turned off to reduce DC power consumption and increase efficiency in the back-off region. The method of improving the linearity of FET amplifiers by offsetting the gate bias to cancel the nonlinearity products is implemented in combination with the efficiency enhancement. For the first time, both techniques are incorporated in the design of a 1.9 GHz CMOS power amplifier that achieves a power-added efficiency (PAE) of 22% at 23-dBm output power. PAE at 6-dB power back-off is measured to be 15%, which exhibits a factor of 2 improvement from the normal class-AB design. Also, third-order intermodulation is improved by approximately 8 dB in the high-power mode of operation when the linearity improvement technique is applied. In addition, this technique does not use transmission line or additional circuits, thus making it ideal for integrated circuit RF power amplifier design.

A new analytical scalable substrate network model for RF MOSFETs

In this work, the substrate parameter scalability of multi-finger RF MOSFET is analyzed and modeled for a broad range of device periphery from 200 /spl mu/m up to 6 mm. For the first time, a new analytical substrate network model based on device geometry of 0.4-/spl mu/m thick-oxide NMOS transistors with ring-shaped substrate contact surrounding the device is proposed. The effect of substrate coupling from the drain and source junctions to the top and bottom substrate contacts has not been considered previously in the conventional MOSFET substrate modeling. It is found that this effect dominates the total substrate resistance as device size increases. The new model approximates the distributed substrate coupling effect into vertical and horizontal directions (from the drain and source junctions to the top and bottom substrate contacts, and to the side substrate contacts), and can accurately predict the substrate parameters for a broad range of device periphery. This approximation simplifies the modeling complexity of the distributed substrate coupling and enables the direct calculation of each substrate component from device geometry with great accuracy. The newly proposed analytical substrate model is essential for developing a scalable MOSFET model for high frequency applications.

SiGe HBT power amplifier for IS-95 CDMA using a novel process, voltage, and temperature insensitive biasing scheme

A novel bias current circuitry for SiGe HBT power amplifier which achieves highly predictable stable current under process, voltage, and temperature (PVT) variations is described in this paper. This approach is ideal for mobile applications under extreme operating conditions. The design offers temperature coefficient of 15.7 ppm//spl deg/C and enables the stabilization of efficiency and output power with ease. The concept was applied to a dual stage power amplifier designed for IS-95 CDMA standard. Maximum linear output power of 28.2 dBm with a gain of 28 dB at 2.5V supply voltage was achieved. The power amplifier has shown a very good stable performance under process, supply voltage, and temperature variations.