Sebastien Cremer

Hybrid Silicon Photonic Circuits and Transceiver for 50 Gb/s NRZ Transmission Over Single-Mode Fiber

This paper presents a 50 Gb/s per lane hybrid BiCMOS and silicon photonic integrated circuit for use in fiber optic communications. Fine pitch copper pillars are used to integrate electronics and silicon photonics. The resulting device demonstrates the generation and detection of up to 56 Gb/s NRZ optical signals over 2-km standard single-mode fiber at 1310-nm wavelength. At 40 Gb/s, the link operates error free, and at 56 Gb/s well below KR4 RS-FEC operating BER. The power dissipation of TX including CW laser is 600 mW (450-mW driver, 150-mW CW laser), RX is 150 mW, resulting in total per channel of less than 750 mW.

Microscopic model for dielectric constant in metal-insulator-metal capacitors with high-permittivity metallic oxides

A microscopic model for metal-insulator-metal (MIM) capacitors with high permittivity metallic oxides is developed to determine the electric field dependence of dielectric constant. The model indicates that the metallic cation displacement in the tetrahedral cell is at the origin of the dielectric constant variations. The temperature dependence has also been included to compare the model with experiment and to give an indication of the reliability of the model. The experimental data that are compared to our model have been obtained from capacitance versus voltage (C-V) characterization on MIM capacitors with alumina as dielectric and TiN electrodes. The C-V curves have been performed at a frequency of 100kHz for different temperatures ranging from 200to400K.

Silicon Photonics R&D and Manufacturing on 300-mm Wafer Platform

Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated.

Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform

A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.

Technology-circuit convergence for full-SOC platform in 28 nm and beyond

In this paper, we present a process/design co-optimization methodology for a full-SOC platform based on 28nm LP CMOS technology with high-k metal-gate (HK/MG) architecture. We report a CPU critical path speed enhancement by implementing a triple gate oxide scheme (so called 28LPG) on HK/MG scheme combined with 20fF/um2 MiM solution for decoupling capacitance. Beside digital speed, we developed a complete RF devices suite enabling high performance analog cells as LNA and VCOs. A 3D integration for high data rate interfaces as wide IOs has been demonstrated based on TSV (Through-Silicon-Via) architecture. Finally ultimate solution for ultra-low power and large memory size is proposed with embedded DRAM offering.

COLK cell : A new embedded DRAM architecture for advanced CMOS nodes

This paper deals with a new and low cost embedded DRAM (eDRAM) architecture. COLK (Capacitor Over Low K) cell with capacitor placed in the first and thick SiO2 dielectric has been successfully integrated. 4Mb eDRAM testchip using this new architecture is functional in 45nm node and presents good yield. Moreover we succeed to demonstrate the capability to continue downscaling of eDRAM for nodes down to 32nm and 22nm.

Realization of back-side heterogeneous hybrid III-V/Si DBR lasers for silicon photonics

In this paper, the simulation, design and fabrication of a back-side coupling (BSC) concept for silicon photonics, which targets heterogeneous hybrid III-V/Si laser integration is presented. Though various demonstrations of a complete SOI integration of passive and active photonic devices have been made, they all feature multi-level planar metal interconnects, and a lack of integrated light sources. This is mainly due to the conflict between the need of planar surfaces for III-V/Si bonding and multiple levels of metallization. The proposed BSC solution to this topographical problem consists in fabricating lasers on the back-side of the Si waveguides using a new process sequence. The devices are based on a hybrid structure composed of an InGaAsP MQW active area and a Si-based DBR cavity. The emitted light wavelength is accordable within a range of 20 nm around 1.31μm thanks to thermal heaters and the laser output is fiber coupled through a Grating Coupler (GC). From a manufacturing point of view, the BSC approach provides not only the advantages of allowing the use of a thin-BOX SOI instead of a thick one; but it also shifts the laser processing steps and their materials unfriendly to CMOS process to the far back-end areas of fabrication lines. Moreover, aside from solving technological integration issues, the BSC concept offers several new design opportunities for active and passive devices (heat sink, Bragg gratings, grating couplers enhanced with integrated metallic mirrors, tapers…). These building boxes are explored here theoretically and experimentally.

Modeling the Mismatch of High-k MIM Capacitors

In this contribution we investigate the matching properties of modern high-k metal-insulator-metal (MIM) capacitors. In particular, we derive a compact physics-based model in order to explain the observed geometry dependence of mismatch. This model is successfully applied to MIM devices processed with Ta₂O₅ and AI₂O₃ as dielectrics.

Design of integrated capacitive modulators for 56Gbps operation

We present TCAD simulation results for the integration of capacitive modulators in a 300mm SOI platform. We show that tuning the capacitor oxide thickness improves the bandwidth and the component efficiency, leading to 860μm active length, 56Gbps data rate and low power consumption (1.2Vpp).

A predictive analytical model of 3D MIM capacitors for RC IC

This paper reports a predictive analytical transmission RLC model of 3D MIM capacitors in a 0.13 mum BICMOS technology. The aim of this predictive model is to help circuit design with compatible CPU time. It allows adjusting process parameters in order to optimize electrical features. The model has been compared with electromagnetic simulations and S-parameters measurements up to 42 GHz.