Nga P. Pham

Sloped Through Wafer Vias for 3D Wafer Level Packaging

Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. Many TSV approaches that have been demonstrated are application specific; and there is a great need for generic solutions. This work describes the design, fabrication and characterization of a TSV technology for silicon substrates where the interconnects are fabricated typically after standard CMOS processing and can be applied to any silicon based technology. This so-called 3D Wafer Level Packaging (3D-WLP) technology die stacking is based on a the thinning first, via last approach: the via is fabricated from the backside of a thinned wafer. Plasma etching of the wafer is used to achieve sloped profde which allows the conformal deposition of the dielectric layer and copper seed metallization. The vias are isolated from the substrate using polymer dielectrics; and spray coating of photoresist is used to pattern the dielectric within the vias. Electrical connection between the front and the back of the wafer is achieved by partial filling of the vias with copper. All processes employed in the fabrication of sloped through wafer vias are performed using standard wafer handling and at low temperature (< 250degC) for post CMOS compatibility. Various dimensions of TSVs are fabricated and electrically characterized by four point measurements. The measurements and calculations on daisy chains connecting a number vias in series show that the via resistance is in the range of 20-30mOmega depending on the via size. We believe that this generic 3D-WLP via approach is suitable for many 3D applications.

Development of vertical and tapered via etch for 3D through wafer interconnect technology

Two types of dry silicon etch techniques are developed to cover two different areas of demand for interconnect technology: one for high aspect ratio (AR) vertical vias and one for tapered vias. Various sizes of vertical vias and trenches with diameters/widths ranging from 1-100 mum with an AR up to 50 are realized using Bosch deep reactive ion etch (DRIE) process. A linear model is applied to describe and to give physical insight in the aspect ratio dependant etch (ARDE) effect. The feasibility of the vertical vias as electrical interconnect is shown by isolating them from the substrate by silicon oxide and then filling with polysilicon. The tapered vias are typically post-processed on fabricated device wafers, making it inherently a more generic approach where diameter size can be large and low AR can be tolerated. Vias with a depth of ~100 mum and a diameter of ~50mum at the bottom (though larger at top) are realized. Varying various etch parameters, slope angles of 70deg-80deg are realized to allow for conformal deposition of dielectric/seed materials on the sidewalls and to allow lithography within the via. Reactive ion etch (RIE) is used to fabricate sloped vias by simultaneously applying etch and passivation gasses. Negative angles on the via top and sidewall roughness are observed that introduce conformal coating problems and increased leakage currents. Smoothening techniques using maskless wet and dry silicon etching are investigated to overcome these problems.

Parylene N as a dielectric material for through silicon vias

This paper reports on the feasibility of parylene N as a dielectric material for through silicon vias (TSV). TSV are the key enabling technology for 3D wafer laver packaging. Parylene is used as an insulating material in one of the approaches adopted for realizing 3D wafer level packaging at IMEC. This paper discusses main issues regarding the processing of parylene N for the TSV application. First, the thickness uniformity of as-deposited parylene across the wafer and inside the via is investigated. The results show that for 200 mm wafers, within-wafer and wafer-to-wafer thickness is sufficiently uniform. The 1-sigma thickness variation of less than 4 percent for both cases is measured. 1 sigma thickness variation of less than 5 percent is observed from batch to batch. Second, the effect of substrate, temporary glue layer and carrier wafer for thinned device wafers on the dry etching of parylene is analyzed. The experiments show that the etching was sufficiently uniform across the wafer; and the uniformity across the surface is recorded to be greater than 95 percent. There is no considerable effect of substrate or bonding layer thickness, however carrier wafer influence the etching rate.

MEMS packaging and reliability: An undividable couple

This paper reviews various approaches to package MEMS, illustrated mainly with examples from imec. Wafer-level or 0-level packaging is mostly dealt with. The role the package plays in achieving the required performance and reliability characteristics is elucidated. Package requirements, such as hermeticity and strength, are named, discussed and illustrated with examples. Considerations of reliability testing are presented. It is made conceivable that vacuum maintenance of tiny MEMS packages is a dominant reliability issue, something not at all obvious to achieve.

Spray coating of photoresist for realizing through-wafer interconnects

Three dimensional (3D) integration requires a through-wafer interconnects, i.e. an integration of electrical connection from one side of the wafer to the other side. In some cases, it involves the lithographic patterning over high topography. For this step, a conformal coating of resist layer is necessary. In this paper, a spray coating process of AZ4562 resist has been investigated. The process is developed in an EVG 101 system on 200mm wafers. Parameters of the spray process such as resist solution, nozzle scanning speed and dispense rate have been studied to find out the proper process for the application of through-wafer interconnects. Some limitations for patterning inside the vias such as flowing of resist, resolution loss of pattern are also discussed and solutions to overcome these limitations are proposed.

Wafer bow of substrate transfer process for GaNLED on Si 8 inch

This paper investigates the wafer bow induced during the substrate transfer process for GaN LED on Si (111) 8 inch wafers. The substrate transfer process is to transfer the thin GaN LED device layer to a carrier wafer using a CuSnCu permanent bonding layer. The process generates tensile bow on a wafer due to the high tensile stress of the Cu or the CuxSny intermetallic layer after bonding. Understanding the wafer bow evolution during the substrate transfer is very important to get a good control of the process. The high wafer bow value may cause problems for some automatic handling tools in the production line or affect process quality such as in lithography. The influence of substrate thickness and Cu metallization thickness on the wafer bow has been studied. A bow compensation layer can be used to compensate the tensile bow, thus minimizing the wafer bow after the substrate transfer process.

Diamond bit cutting for processing high topography wafers

In this paper we report the results of diamond bit cutting on metals, such as Cu and Sn, polymers, temporary glue and polyimide. Diamond bit cutting is an attractive, fast and economically viable option when processing on high topography wafers is required, or when smooth surface finish is required. Diamond bit cutting can planarize the surface of the high topography features on which conventional IC processing steps can be performed with ease.

Thermo-mechanical design of a generic 0-level MEMS package using chip capping and Through Silicon Via's

This paper describes the thermo-mechanical design of an advanced zero-level capping technology used for packaging of a MEMS die. The package approach uses Intermetallic Compound (IMC) bonding to seal the MEMS die with a cap, and uses Through Silicon Vias (TSV) to provide the electrical connections from the MEMS die to the second level substrate (LTCC or PCB). Advanced FEM based thermo-mechanical simulations are performed to estimate the impact of processing and temperature cycling on the mechanical stresses and deformations induced in the structure. Special focus goes to the rigid CuSn IMC bond, the copper TSV using a polymer dielectric and the cap deflection under a pressure of 1 bar (vacuum inside) and 90 bar (simulating overmoulding). Finally, the impact of assembling the MEMS package on an LTCC substrate and an FR4 printed circuit board with CuSn, respectively solder connections is investigated with respect to the package reliability, the cap deflection and the strain and anchor rotation at location of the MEMS.

Metal-bonded, hermetic 0-level package for MEMS

This paper presents a zero-level packaging technology for hermetic encapsulation of MEMS. The technology relies on the “chip capping” of the MEMS using a metallic bond made by means of diffusion soldering of a Cu-Sn system at a temperature of around 250°C. For this, on a “capping wafer” a sealing ring (or bond frame), composed of a double layer of Cu/Sn, is grown, and on the MEMS wafer a matching ring of a single Cu layer is made. Next, the “capping chip” is assembled onto the “MEMS die”, either in a die-to-wafer (D2W) or a wafer-to-wafer (W2W) fashion. The thicknesses of the layers (Cu/Sn and Cu) and the bonding process parameters (temperature and force profile) have been optimized so as to achieve a strong, hermetic package, that remains stable up to temperatures as high as ∼415°C. Leak testing, based on the “membrane deflection method”, revealed that the packages are air tight and He leak tight. No noticeable change of the deflection of the cap (thinned down to 20–50 µm) was observed as a result of pressurizing the packages for 11 days under He at 30 MPa.

Lithography for Patterning inside through-Si Vias

Lithographic patterning inside through Si vias (TSV) requires conformal coating of resist over high topography and exposure with a large gap distance. This paper investigates some parameters that have an effect on the resist pattern definition at the bottom of ~100 mum deep via. The influences of the large gap exposure, resist thickness and resist type to the dimension of resist patterns have been studied. The relation of resist thickness to the size of the Si vias is also reported. Finally, an example of patterned resist inside via as a masking layer for dielectric patterning is presented as well.