Niladri Narayan Mojumder

Holistic technology optimization and key enablers for 7nm mobile SoC

We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (R_wire) multiplied by logic gate input pin cap (C_pin), R_wire×C_pin, is identified as a major limiter of performance and power at N7. Reducing C_pin is crucial to mitigate abruptly rising BEOL R_wire effect. Depopulation of fin is one of most effective methods to reduce C_pin, and scale the logic gate area. Air Spacer (AS) on transistor sidewall is proposed to further reduce C_pin, whose benefit is enhanced by reduction of other C_pin components. Careful choice of routing metal stack ameliorates adverse effect of R_wire. Wrap-Around-Contact (WAC) over Source and Drain of scaled fin pitch (P_fin) is needed to reduce transistor resistance (R_tr). Fin depopulation with other cost effective process innovations significantly improve Power-Performance-Area-Cost (PPAC) of N7, enabling continued scaling of mobile System on a Chip.

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization

We present, for the first time, a holistic data-path driven transistor-interconnect co-optimization method, which systematically isolates the logic-gate and interconnect-wire dominated data-paths in block-level delay-bins (i.e., sub-binning of delay based bins) to significantly improve accuracy of static and dynamic power estimation. It captures the critical interdependence of transistor architecture (FEOL) including local interconnect, and BEOL metal stack optimization to achieve holistic 10nm (N10) technology optimization at target speeds. Using the proposed method, we drive >2.5x Performance/Watt (PpW) improvement for N10 FinFET SOC design over 14nm (N14). Even with ∼3x higher wire resistance of min metal width, the PpW @target-speed for N10 improves >2.5x over N14 with proper design of metal/via stack, transistor Vt and fin-profile as well as standard-cell architecture. Reducing active fin-count and routing distance between standard-cells is a critical design knob for N10 mobile SOC enablement. The proposed methodology enables smartphone-usage (days-of-use) based technology optimization, driving longer battery-life in mobile SOCs, keeping process cost and complexity at minimum.