Niti Goel

InGaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectric grown by atomic-layer deposition

The influence of various process conditions on the structural integrity and electrical properties of Al∕HfO2∕p-In0.13Ga0.87As metal-oxide-semiconductor capacitors was investigated. Room temperature capacitance voltage measurements revealed postdielectric deposition anneal reduced hysteresis by more than 0.5V and sulfur passivation of InGaAs improved the capacitance frequency dispersion properties as well as reduced interface trap density. At V=VFB−1V, the leakage current densities ∼1.3×10−7, 0.4×10−6, and 1.3×10−6A∕cm2 were measured in devices with annealed HfO2 (110 and 32A) and sulfur-passivated InGaAs (110A unannealed HfO2), respectively. Transmission electron microscopy revealed sharp epitaxial InGaAs/crystalline HfO2 and GaAs∕InGaAs interfaces.

In0.53Ga0.47As based metal oxide semiconductor capacitors with atomic layer deposition ZrO2 gate oxide demonstrating low gate leakage current and equivalent oxide thickness less than 1nm

The paper demonstrates properties of metal oxide semiconductor capacitors fabricated on molecular beam epitaxial In0.53Ga0.47As wafers with the atomic layer deposition ZrO2 gate oxide. The equivalent oxide thickness of 0.8nm was obtained for 5nm thick ZrO2, while the gate leakage current density at VFB+1V was as low as 0.1A∕cm2. Sensitivity of capacitance-voltage characteristics to the metal gate work function along with low frequency dispersion of ∼5%/decade served as a strong evidence of a nonpinned Fermi level at the oxide-InGaAs interface. Both electrical and structural properties remain stable up to 800°C.

Band offsets of atomic-layer-deposited Al2O3 on GaAs and the effects of surface treatment

The metal gate/high-k dielectric/III-V semiconductor band alignment is one of the most technologically important parameters. We report the band offsets of the Al/Al2O3/GaAs structure and the effect of GaAs surface treatment. The energy barrier at the Al2O3 and sulfur-passivated GaAs interface is found to be 3.0±0.1 eV whereas for the unpassivated or NH4OH-treated GaAs is 3.6 eV. At the Al/Al2O3 interface, all samples yield the same barrier height of 2.9±0.2 eV. With a band gap of 6.4±0.05 eV for Al2O3, the band alignments at both Al2O3 interfaces are established.

Self-aligned n-channel metal-oxide-semiconductor field effect transistor on high-indium-content In0.53Ga0.47As and InP using physical vapor deposition HfO2 and silicon interface passivation layer

In this work, we present the electrical and material characteristics of TaN∕HfO2∕In0.53Ga0.47As and InP substrate metal-oxide-semiconductor capacitors and self-aligned n-channel metal-oxide-semiconductor field effect transistor (n-MOSFET) with physical vapor deposition Si interface passivation layer. Excellent electrical characteristics, thin equivalent oxide thickness (∼1.7nm), and small frequency dispersion (<2%) were obtained. n-channel high-k InGaAs- and InP-MOSFETs with good transistor behavior and good split capacitance-voltage (C-V) characteristics on In0.53Ga0.47As and InP substrates have also been demonstrated.

High-indium-content InGaAs metal-oxide-semiconductor capacitor with amorphous LaAlO3 gate dielectric

The structure and electrical properties of LaAlO3∕n-In0.53Ga0.47As metal-oxide-semiconductor capacitors deposited by molecular-beam epitaxy were investigated. Transmission electron microscopy revealed a sharp interface between the dielectric and InGaAs. Postdeposition annealing at 440–500°C significantly reduced the capacitive equivalent thickness and frequency dispersion. A hysteresis of 15mV–0.1V, a dielectric permittivity of 17±1, and a dielectric strength of ∼4.3MV∕cm were measured. Additionally, a high loss in the parallel conductance and gate-bias independence in the inversion region was observed, implying the fast generation rate of minority carriers in In0.53Ga0.47As.

High performance In0.7Ga0.3As metal-oxide-semiconductor transistors with mobility >4400 cm2/V s using InP barrier layer

We have investigated device performance for In0.7Ga0.3As and In0.53Ga0.47As metal-oxide-semiconductor transistors (MOSFETs) with and without InP barrier layer using atomic layer deposited Al2O3 gate dielectric. InP barrier layer was found to provide higher transconductance for both In0.7Ga0.3As and In0.53Ga0.47As MOSFETs, especially for In0.7Ga0.3As. In0.7Ga0.3As MOSFETs with InP barrier layer show much higher transconductance and lower subthreshold swing than other MOSFETs studied. These In0.7Ga0.3As MOSFETs exhibit high drive current of 98 mA/mm (L=20 μm), subthreshold swing of 106 mV/decade and maximum effective channel mobility of 4402 cm2/V s.

Synchrotron radiation photoemission spectroscopic study of band offsets and interface self-cleaning by atomic layer deposited HfO2 on In0.53Ga0.47As and In0.52Al0.48As

The Synchrotron Radiation Photoemission Spectroscopic (SRPES) study was conducted to (a) investigate the surface chemistry of In{sub 0.53}Ga{sub 0.47}As and In{sub 0.52}Al{sub 0.48}As post chemical and thermal treatments, (b) construct band diagram and (c) investigate the interface property of HfO{sub 2}/In{sub 0.53}Ga{sub 0.47}As and HfO{sub 2}/In{sub 0.52}Al{sub 0.48}As. Dilute HCl and HF etch remove native oxides on In{sub 0.53}Ga{sub 0.47}As and In{sub 0.52}Al{sub 0.47}As, whereas in-situ vacuum annealing removes surface arsenic pile-up. After the atomic layer deposition of HfO{sub 2}, native oxides were considerably reduced compared to that in as-received epi-layers, strongly suggesting the self-clean mechanism. Valence and conduction band offsets are measured to be 3.37 {+-} 0.1eV, 1.80 {+-} 0.3eV for In{sub 0.53}Ga{sub 0.47}As and 3.00 {+-} 0.1eV, 1.47 {+-} 0.3eV for In{sub 0.52}Al{sub 0.47}As, respectively.

Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

We present the first demonstration of a III–V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III–V and Si devices can be processed side by side in the same Si fabrication line The L<inf>g</inf> = 500 nm device has a excellent drive current of ∼450 µA/µm and intrinsic transconductance of ∼1000 µS/µm indicating that III–V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.

InGaAs MOSFET performance and reliability improvement by simultaneous reduction of oxide and interface charge in ALD (La)AlOx/ZrO 2 gate stack

The performance and reliability of ZrO<inf>2</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs are shown to be improved by simultaneous reduction of dielectric and interface charges. An amorphous (La)AlO<inf>x</inf> interlayer at the ZrO<inf>2</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As interface is a key to reduce border traps, interface traps and move ZrO<inf>2</inf> fixed charge away from the In<inf>0.53</inf>Ga<inf>0.47</inf>As. Border traps are reduced ∼3x, effective fixed charges are reduced ∼3x and interface trap density is reduced ∼1.5x. The net effect of the improved stack is 50% normalized I<inf>d</inf> improvement and 75% normalized G<inf>m</inf> improvement. P/NBTI cyclic stress results indicate Al<inf>2</inf>O<inf>3</inf>/ZrO<inf>2</inf> is more reliable than ZrO<inf>2</inf> only. ΔV<inf>th</inf> of the bilayer show excellent repeatability; conversely, ΔV<inf>th</inf> of ZrO<inf>2</inf> shows permanent (not recoverable) interface degradation during relaxation (NBTI stress). La incorporation in Al<inf>2</inf>O<inf>3</inf> increases the к-value while providing improved reliability over both the ZrO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf>/ZrO<inf>2</inf> stack.

Addressing the gate stack challenge for high mobility In x Ga 1-x As channels for NFETs

Through a detailed evaluation of various dielectrics, we address the primary challenges associated with gate stacks on high electron mobility InGaAs channels. More specifically we address key gate stack issues including a) EOT scalability for high performance and electrostatic control (this work CET ~0.78 nm) with acceptable leakage both at operating and offstate for low power (this work Jg ~1 A/cm2), b) understand source and impact of charge trapping, c) thermal stability on InGaAs, and d) impact of In% on interface structure and its impact on surface channel MOSFETs.