Nobuaki Yasutake

Impact of BOX scaling on 30 nm gate length FD SOI MOSFET

This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T/sub BOX/ is varied from 5 nm to 145 nm. In addition, optimum design regions of T/sub BOX/ for achieving performance requirements are demonstrated.

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.

14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide

High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire a shallow source/drain (S/D) extension profile, the optimization of a low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes the gate depletion effect, so that a high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using an offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.

In situ Doped Embedded-SiGe Source/Drain Technique for 32 nm Node p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor

The impacts of source and drain (S/D) doping on device performance in embedded SiGe (e-SiGe) p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) are presented. An in situ boron-doped e-SiGe S/D device exhibits higher drive current than a boron-implanted e-SiGe S/D device owing to its enhanced hole mobility and reduced parasitic resistance. The precise control of the recessed Si shape and the SiGe proximity to the channel is essential for utilizing the intrinsic benefit of an in situ boron-doped e-SiGe S/D. Moreover, it was confirmed that the channel stress induced by e-SiGe S/D increases as MOSFET size decreases. This indicates that the use of in situ boron-doped e-SiGe S/D is a promising technique for 32 nm node pMOSFET.

Comprehensive performance assessment of scaled (110) CMOSFETs based on understanding of STI stress effects and velocity saturation

We present the systematic study on dominant factors of the performance of scaled (110) n/pFETs. STI stress effects and velocity saturation phenomena in narrow and short (110) devices are investigated for the first time. Idsat of scaled (110) nFETs approaches (100) nFETs as a result of mu increase due to transverse compressive stress from STI in (110) nFETs and strong velocity saturation in (100) nFETs. Meanwhile, Idsat of scaled (110) pFETs are still superior to (100) pFETs due to high mu of (110) pFETs and weaker velocity saturation than nFETs as long as Rsd of (110) pFETs is well suppressed. As a result, scaled (110) CMOS shows excellent performance even without intentional stressors.

Understanding of strain effects on high-field carrier velocity in (100) and (110) CMOSFETs under quasi-ballistic transport

We systematically study the strain effects on high-field carrier velocity (v) in (100) and (110) short-channel n/pFETs by means of substrate bending experiment. v and I<inf>dsat</inf> increase by strain is determined not only by low-field mobility (μ) enhancement (Δμ/μ) but also by the modulation of saturation velocity (v<inf>sat</inf>). It is found that v<inf>sat</inf> increases more by strain in smaller-Δμ/μ devices. The difference of Δμ/μ is compensated by v<inf>sat</inf> change. As a result, Δv/v of (100)/(110) n/pFETs converge in sub-30nm regime. The superiority of (110) CMOS to (100) CMOS is maintained in terms of both I<inf>dlin</inf> and I<inf>dsat</inf> at highly-strained conditions.

Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology

Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, record high drive current of 714 muA/mum at Vdd=1.0 V, Ioff =100 nA/mum at 24 nm gate length, is demonstrated.

Insight into the S/D engineering by high-resolution imaging and precise probing of 2D-carrier profiles with scanning spreading resistance microscopy

For the first time, high-resolution carrier imaging has been carried out on (110)/(100) pFETs and nFETs with scanning spreading resistance microscopy (SSRM). The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron I/I. Direct evidence has been shown that As out-diffusion under NiSi made conductive paths that degrade junction leakage on (110) nFETs. The Si:C influences on S/D profiles are also directly observed. We also succeeded in a full-FIB sample-making for the first time, showing the high potential of SSRM technology for further scaled devices.

A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe -source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved comparing with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451muA/mum at verbar;Vdd| of 0.9V, Ioff of 100 nA/mum (552 muA/mum at |Vdd | of 1.0V). Furthermore, by combining with Vdd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation

High-resolution and site-specific SSRM on S/D engineering

Recently, we reported significantly improved spatial resolution in scanning spreading resistance microscopy (SSRM) by measuring in a vacuum. In this work, we demonstrate the 1-nm-spatial resolution of SSRM on pn junction delineation by comparing with three-dimensional device simulation. A five-order dynamic range of carrier concentration is also confirmed on staircase sample. A systematic comparison between pFETs/nFETs on (110) and (100) substrates has been carried out with SSRM. The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron ion implantation. We also succeeded in a new sample-making method by fully FIB pick up, enabling site-specific SSRM characteristics for failure analysis and for further scaled devices.