Takanori Sutou

UV NIL template making and imprint evaluation

UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the finest patterns. We have been focused on the resolution improvement in mask making, and with a 100keV acceleration voltage spot beam EB writer process, we have achieved down to 16nm resolution, and have established a mask making process to meet the requirements of the pioneers. Usually such masks needed just a small field (several hundred microns square or so). At the same time, UV NIL exploration has reached the step of feasibility study for mass production, and full chip field masks have been required, though the resolution demand is not as tough as for the extremely advanced usage mentioned above. The 100kV EB writers are adopting spot beams to generate the pattern and have a fatally low throughput if we need full chip writing. So for full chip masks, we have started the adoption of 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing In this paper, we will show latest results both with the 100kV spot beam writer and the 50keV VSB EB writers. With the 100kV spot beam writer, we achieved 16nm resolution, but found that to achieve further improvement, an innovation in pattern generation method or material would be inevitable. With the 50kV VSB writers, we could generate full chip pattern in a reasonable time, and by choosing the right patterning material and process, we could achieve resolution down to 32nm. Our initial results of 32nm class NIL masks with full chip field size will be shown and resolution improvement plan to further technology nodes will be discussed. Eventually, NIL is coming closer to production stage. We will also start the discussion about the infrastructures necessary for NIL mask manufacturing in this paper.

Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability

Double patterning technology (DPT) is one of the most practical candidate technologies for 45nm half-pitch or beyond while conventional single exposure (SE) is still dominant with hyper NA avoiding DPT difficulties such as split-conflict or overlay issue. However small target dimension with hyper NA and strong illumination causes OPC difficulty and small latitude of lithography and photomask fabricated with much tight specification are required for SE. Then there must be double patterning (DP) approach even for SE available resolution. In this paper DP for SE available resolution is evaluated on lithography performance, pattern decomposition, photomask fabrication and inspection load. DP includes pattern pitch doubled of SE, then lithography condition such as mask error enhancement factor (MEEF) is less impacted and the lower MEEF means less tight specification for photomask fabrication. By using Synopsys DPT software, there are no software-induced conflicts and stitching is treated to be less impact. And also this software detects split-conflicts such as triangle or square placement from contact spacing. For estimating photomask inspection load, programmed defect pattern and circuit pattern on binary mask are prepared. Smaller MEEF leads less impact to defect printing which is confirmed with AIMS evaluation. As an inspection result, there are few differences of defect sensitivity for only dense features and also few differences of false defect counts between SE and DP with less NA. But if higher NA used, DPs inspection sensitivity is able to be lowered Then inspection load for DP would be lighter than SE.

Pattern decomposition for double patterning from photomask viewpoint

Double Patterning Technology (DPT) has been evaluated and reported since 32nm half pitch is recognized to be required with conventional immersion ArF lithography. DPT requires pattern decomposition into two pattern sets and the decomposition becomes more complex for especially so-called logic pattern including irregular pattern placement and many-vertices polygons. The innocent decomposition often creates forced segmentation of those polygons and two different aspect of photomasks such as density or substantial line direction. Those decomposed photomasks not only produce large possibilities of different error behavior but also leave annoyance complexity untouched. It is well known that line-ends and dense twisted lines produce large MEF. Then tighter specification for photomask fabrication have been required since the resolution limit was getting below the exposure wavelength. So the decomposition that creates tight patterns into separate two photomasks has possibilities of the fabrication load lighter. In this paper, the decomposition of criteria for DPT which helps photomask fabrication with a small possibilities is evaluated and discussed. Furthermore though its getting to popular that overlay and CD uniformity of photomasks for DPT impact to completed CD with wafer exposure directly, considering other errors such as CD shift or phase error which are supposed to recover by exposure in addition to those errors are also studied.

In-field CD uniformity control by altering transmission distribution of the photomask, using Ultra fast pulsed laser technology

As pattern feature sizes on the wafer become smaller and smaller, requirements for CD variation control has become a critical issue. In order to correct CD uniformity on the wafer, the DUV light transmission distribution of the photomask was altered using an ultra-fast pulsed laser technology. By creating a small scattering pixel inside the quartz body of the mask, a multitude of such points creates Shading Elements inside the quartz according to a predetermined CD variations distribution map. These Shading Elements reduce the dose of scanners laser illumination onto the wafer per a local area. Thus by changing the local light intensity, inside the exposure field, to a required level during the photolithographic process the wafer CD is changed locally inside the field. This complete process of writing a multitude of Shading Elements inside the mask in order to control the light transmission and hence wafer level CD locally is called the CD Control (CDC) process. We have evaluated the tool utilizing Ultra fast laser pulses (CDC 101) for local transmission and CD controllability on the wafer. We used Binary and Att-PSM test masks and three kinds of test patterns to confirm the sensitivity of transmission and CD change by the attenuation levels of Shading Elements which is sequentially changed from 0% to 10%. We will compare the AIMS results to printed CD on wafer or simulation results, so that we can correlate the transmission change and CD change by the attenuation levels. This paper also reports the CD uniformity correction performances by using attenuation mapping method on Binary mask. We also cover how Shading Elements affect the phase and transmission on the Att-PSM.

Lithographic performance comparison with various RET for 45-nm node with hyper NA

In order to realize 45 nm node lithography, strong resolution enhancement technology (RET) and water immersion will be needed. In this research, we discussed about various RET performance comparison for 45 nm node using 3D rigorous simulation. As a candidate, we chose binary mask (BIN), several kinds of attenuated phase-shifting mask (att-PSM) and chrome-less phase-shifting lithography mask (CPL). The printing performance was evaluated and compared for each RET options, after the optimizing illumination conditions, mask structure and optical proximity correction (OPC). The evaluation items of printing performance were CD-DOF, contrast-DOF, conventional ED-window and MEEF, etc. Its expected that effect of mask 3D topography becomes important at 45 nm node, so we argued about not only the case of ideal structures, but also the mask topography error effects. Several kinds of mask topography error were evaluated and we confirmed how these errors affect to printing performance.

45-32-nm node photomask technology with water immersion lithography

As for 32-nm node (minimum half pitch 45-nm) logic device of the next generation, the leading semiconductor device makers propose the following three kinds of lithography techniques as a candidate, multi-exposure with water immersion lithography. So we will evaluate them. In previous work, we evaluated the resolution limit and printing performance through various pitches of 45-nm node (minimum half pitch 65-nm) lithography. We evaluated the alternate aperture phase shift mask(alt-PSM) of NA=0.93 (dry and immersion) and various resolution enhancement technologies (RETs) with off-axis and polarized illumination of NA=1.07(water immersion). The minimum k1 examined at previous time was 0.31 and 0.39 respectively. To achieve 32-nm node of the next generation with water immersion lithography, we must use higher NA but yet severe k1. The combination of the strong RET, polarization and multi-exposure is thought to be required. In order to resolve severe k1 (<0.3), the double patterning is thought as a promising candidate technology, though the disadvantageous points will appear such as very severe alignment accuracy and the twice process of wafer. In this report, we will discuss some RETs such as double dipole lithography(DDL), double patterning lithography(DPL) and alt-PSM that have sufficient printing performance through various pitches of 32-nm node. We evaluate the effect and the performance of the selected lithography side RETs and mask material RETs for each, using optical simulation software.

UV NIL mask making and imprint evaluation

UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the finest patterns. We have been focused on the resolution improvement in mask making, and with a 100kV acceleration voltage EB writer process, we have achieved down to 18nm resolution, and have established a mask making process to meet the requirements of the pioneers. Usually such masks needed just a small field (several hundred microns square or so). Now, UV NIL exploration seems to have reached the step of feasibility study for mass production. Here, instead of a small field, a full chip field mask is required, though the resolution demand is not as tough as for the extremely advanced usage. The 100kV EB writers are adopting spot beams to generate the pattern and have a fatally low throughput if we need full chip writing. In this work, we focused on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing. The 50kV VSB writers can generate full chip pattern in a reasonable time, and by choosing the right patterning material and process, we could achieve resolution down to 32nm. Our initial results of 32nm class NIL masks with full chip field size will be shown and resolution improvement plan to further technology nodes will be discussed.

Estimating DPL photomask fabrication load compared with single exposure

DPL (Double Patterning Lithography) has been identified as one of major candidates for 45nm and 32nm HP since ITRS2006update and several reports of the performance or challenges of DPL have been published. DPL requires at least two photomasks with tighter specification of image placement and the difference of mean to target according to ITRS2006update. On the other hand, approximately half of whole features of single layer are written on each photomask and the densest features are split into other photomask in consequence of pitch relaxation for DPL. Then the photomask writing data of two sets for DPL and single data for single exposure are evaluated for photomask fabrication load. The design will be automatically decomposed with EDA tool and OPC will be tuned as DPL or single exposure. Not only number of fractured features but also feasibility study of automatic decomposition will be presented and discussed. The consequences of relaxed pitch on process, inspection, repair, yield, MEEF and cycle time will be discussed with results as available.

Mask CD compensation method using diffraction intensity for lithography equivalent metrology

In 45nm node and beyond, since mask topography effect is not ignorable, 3D simulation is required for precise printing performance evaluation and mask CD bias optimization. Therefore, the difference between real mask and 3D mask model on simulation needs to be clarified. Verification of 3D mask model by diffraction intensity measurement with AIMSTM45-193i was discussed in our previous works. In various conditions (mask materials, pattern dimensions and CD-SEMs), the diffraction intensity measured on actual masks were agreed to 3D simulations by introducing constant CD offset. The cause of the CD difference was explained to be mainly due to electron beam size by using simple SEM image simulation. In this work, we introduce the new procedure to measure diffraction intensity by AIMSTM in order to confirm the CD difference between 3D mask model and CD-SEM more accurately because the agreement of diffraction intensity between AIMSTM and simulation was not perfect especially for 1st orders diffraction. As a result, the value of CD difference was slightly changed on the same mask by using the same CD-SEM. Measured diffraction intensity showed better matching to 3D simulation results with the constant CD offset on all evaluated conditions. Secondary, to confirm how accurately printing performance could be predicted by CD-SEM measurement results, MEEF difference calculated from diffraction intensity between 3D simulation and CD-SEM with the offset was confirmed. Additionally, this method was extended to hole patterns. Measured diffraction intensity was matched to simulation result with the same CD offset with line/space patterns and appropriate corner rounding.

Extendibility of single mask exposure for practical ArF immersion lithography

The ArF water immersion is one of the most promising candidate technologies for 45-nm node lithography. But it have been predicted that the realization of 32-nm node (minimum half pitch 45nm) is very difficult when using the water immersion of 1.35 NA and single mask exposure. Therefore, some double-exposure technologies are expected for 32-nm node logic device. However, the single mask exposure would be expected because it has very big advantage of short process time and/or cost etc., compared to other double-exposure methods. In this research, we evaluated two NA setting of ArF immersion as the models and the required structure and error budget of photomasks. One is the maximum NA of water immersion (= 1.35) and another is using high refractive index materials with NA of 1.55. The lithographic performance was evaluated for line and space pattern through various pattern pitches with optical proximity correction (OPC). The evaluation items of printing performance are CD-DOF, contrast-DOF and MEEF, etc. The suitable kind of mask and structure are also considered with effect of several kinds of mask topography error. The limit of single mask exposure will be examined by setting the restriction such as minimum half pitch and so on.