Tomoyuki Yamase

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

A low-power dual-band triple-mode WLAN CMOS transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively

A widely tunable CMOS Gm-C filter with a negative source degeneration resistor transconductor

We propose a new negative source degeneration resistor (NSDR) transconductor to achieve a wide continuous-tuning range gm-C filter applicable for IEEE802.11a/b/g wireless-LANs and W-CDMA. The NSDR-transconductor using a source degeneration resistor and positive feedback differential amplifier that acts as a negative resistor. This configuration enables the equivalent source degeneration resistance to be drastically increased without degrading linearity, thus resulting in a wide gm tuning. A 6th -order elliptic low-pass filter using this NSDR-transconductor exhibits a cutoff frequency (f/sub c/) tuning range of 1.5-12MHz, which is two times wider than that of conventional filters. Additionally, we introduce a new figure of merit (FoM) evaluating the basic filter performance. This filter shows 0.35 fj (FoM) in the IEEE802.11a mode, which is, to our best knowledge, the best value in the CMOS channel-select filters.

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

As 40Gb/s optical communication systems enter the commercial stage, the transceiver, which is a key component of these systems, requires lower power dissipation, a size reduction, and a wider frequency range to meet the requirements of several standards, such as OC-768/STM-256 (39.8Gb/s), OTU-3 (43.0Gb/s), and 4×10GbE-LANPHY (44.6Gb/s). 40Gb/s transceivers have already been reported in SiGe-based technology.However, they dissipate more than 10W in total and do not support 39.8-to-44.6Gb/s wide-range operations [1–2]. There have been recent reports on CMOS transceivers, but their speed performance is still less than 40Gb/s and their output signal suffers from large jitter [3–5]. In this paper, 40Gb/s SFI-5-compliant TX and RX chips in 65nm CMOS technology consume 2.8W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40GHz VCO, a 40Gb/s retiming D-FF, and 40GHz clock-distribution circuits that lead to a low jitter of 0.57psrms and 3.1pspp at 40Gb/s. A 40/20GHz clock-timing-adjustment circuit based on a phase interpolator is used to ensure wide-range error-free operations (BER ≪ 10−12) at 39.8 to 44.6Gb/s. A quadruple loop architecture is introduced in the CDR circuit of the RX, resulting in a 38Gb/s error-free operation (BER ≪ 10−12) at 231−1 PRBS with a low rms jitter of 210fs in the recovered clock.

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over the range of 39.8 Gb/s to 44.6 Gb/s with a 231-1 PRBS pattern. The receiver chip operates over the range of 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock is 359 fs to 450 fs. By taking advantage of CMOS technology, each chip achieves low power consumption of 2.8 W and full integration of SFI-5 functions, PRBS generators/error checkers, a DPSK precoder/decoder, and control interfaces in a 4.9 × 5.2 mm2 die.

An FPGA-based all-digital transmitter with 28-GHz time-interleaved delta-sigma modulation

An FPGA-based all-digital transmitter with 28-GHz ΔΣ-modulation is presented. For improving the operation frequency of ΔΣ modulator (DSM), a multi-channel look-ahead time-interleaved ΔΣ modulator is proposed. By implementing the proposed DSM in an FPGA, 28-GHz operation of DSM has been achieved. Furthermore, FPGA-based all-digital transmitter integrating the proposed DSM can satisfy the spectral mask of IEEE 802.11a WLAN standard in 5.2-GHz band. To the best of our knowledge, this is the first demonstration of an FPGA-based all-digital transmitter which can directly generate 5-GHz band WLAN signal.

A digital radio-over-fiber downlink system based on envelope delta-sigma modulation for multi-band/mode operation

A digital radio-over-fiber (DRoF) downlink system using envelope delta-sigma modulation (EDSM) for multimode/band applications is presented. Analyses and simulations reveal that the EDSM scheme increases tolerance to jitter introduced by optical components. This has been verified and demonstrated with a DRoF link using CMOS EDSM IC. As a result of the improvement, this system successfully meets major 3GPP LTE bands from 760 MHz to 2.6 GHz as well as IEEE 802.11g WLAN standard requirement.