Ryo Iida

Sub-10-nm Extremely Thin Body InGaAs-on-Insulator MOSFETs on Si Wafers With Ultrathin

We have demonstrated sub-10-nm extremely thin body (ETB) InGaAs-on-insulator (InGaAs-OI) nMOSFETs on Si wafers with Al₂O₃ ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding process. We have fabricated the ETB InGaAs-OI nMOSFETs with channel thicknesses of 9 and 3.5 nm. The 9-nm-thick ETB InGaAs-OI n MOSFETs with a doping concentration (N_D) of 10¹⁹ cm^-3 exhibit a peak electron mobility of 912 cm²/V·s and a mobility enhancement factor of 1.7 times against the Si nMOSFET at a surface carrier density (N_s) of 3 ×10¹² cm^-2. In addition, it has been found that, owing to Al₂O₃ UTBOX layers, the double-gate operation improves the cutoff properties. As a result, the highest on-current to the lowest off-current (I_on/I_off) ratio of approximately 10⁷ has been obtained in the 3.5-nm-thick ETB InGaAs-OI nMOSFETs. These results indicate that the high-mobility III-V nMOSFETs can be realized even in sub-10-nm-thick channels.

\hbox{Al}_{2}\hbox{O}_{3}

We report that a Ni–InGaAs alloy can be used as a source/drain (S/D) metal for InGaAs metal–oxide–semiconductor field-effect transistors (MOSFETs), allowing us to employ the salicide-like self-align S/D formation. We also introduce Schottky barrier height (SBH) engineering process by increasing the indium content of InxGa1-xAs channels, which successfully reduces SBH down to zero. We propose a fabrication process for self-aligned metal S/D MOSFETs using Ni–InGaAs and demonstrate successful operation of the metal S/D InxGa1-xAs MOSFETs. The In0.7Ga0.3As MOSFETs exhibit an S/D resistance (RSD) that is 1/5 lower than that in P–N junction devices and a high peak mobility of 2000 cm2 V-1 s-1.

Buried Oxide Layers

We have demonstrated extremely-thin-body (ETB) (3.5 and 9 nm) InGaAs-on-insulator (InGaAs-OI) MOSFETs on Si substrates with Al<inf>2</inf>O<inf>3</inf> ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding (DWB). We have found that the ETB highly-doped InGaAs-OI n-channel MOSFETs without p-n junction can perform a normal MOSFET operation under front- and back-gate configuration and the double-gate operation can provide excellent on-current/off-current (I<inf>on</inf>/I<inf>off</inf>) properties of ∼10⁷ and the improved S factor even for InGaAs-OI MOSFETs with ND of 1×10¹⁹ cm⁻³.

Self-Aligned Metal Source/Drain InxGa1-xAs n-Metal–Oxide–Semiconductor Field-Effect Transistors Using Ni–InGaAs Alloy

We clarified that Fermi levels at InGaAs MOS interfaces are pinned inside conduction band (CB) and that this pinning severely degrades the effective mobility. Also, the energy position of the Fermi level pinning (FLP) is found to be tunable. It is experimentally shown that the increase in the difference between the FLP position and the CB minimum (CBM) leads to high mobility at high Ns region. Also, possible physical origin for this FLP is proposed.

Extremely-thin-body InGaAs-on-insulator MOSFETs on Si fabricated by direct wafer bonding

The extremely thin body (ETB) InGaAs-on-insulator (-OI) metal–oxide–semiconductor field-effect transistors (MOSFETs) on Si substrates were demonstrated by using Ni–InGaAs alloy metal source/drain (S/D). It has been found that a light doping concentration of ~1016 cm-3 and indium-rich InGaAs channels (In0.7Ga0.3As) provide a high mobility of 1700 cm2 V-1 s-1 even in the channel thickness of 10 nm. This is the first demonstration of ETB III–V-OI MOSFETs combined with the metal S/D technology. We have also achieved excellent ID–VG characteristics with an Ion/Ioff ratio of over 105 and low SS of 120 mV/dec in 5-nm-thick In0.7Ga0.3As-OI MOSFETs.

Impact of Fermi level pinning inside conduction band on electron mobility of In x Ga 1−x As MOSFETs and mobility enhancement by pinning modulation

The electron mobility enhancement of extremely thin body In0.7Ga0.3As-on-insulator (-OI) metal–oxide–semiconductor field-effect transistors (MOSFETs) on Si substrates by using In0.3Ga0.7As MOS interface buffer layers was demonstrated. The MOSFETs with the InGaAs thickness of 2/5/3 nm have exhibited the electron mobility of 2810 cm2 V-1 s-1 with an enhancement factor of 4.2 against that of Si MOSFET. We have examined the body thickness (Tbody) dependence of the electron mobility. It was found that a channel thickness fluctuation scattering mechanism strongly affects the mobility in Tbody of around 10 nm and thinner. The formation of a uniform and flat InGaAs-OI wafer is required for further improvements.

High Performance Extremely Thin Body InGaAs-on-Insulator Metal?Oxide?Semiconductor Field-Effect Transistors on Si Substrates with Ni?InGaAs Metal Source/Drain

We have studied the formation of III?V-compound-semiconductors-on-insulator (III?V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III?V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O2?plasma-assisted DWB process with ECR sputtered SiO2?BOX layers and a DWB process based on atomic-layer-deposition Al2O3?(ALD-Al2O3) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO2?and ALD-Al2O3?BOX layers are desorption of Ar and H2O gas, respectively. In order to suppress micro-void generation in the ECR-SiO2?BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al2O3?BOX layers to increase the deposition temperature of the ALD-Al2O3?BOX layers. It is also another possible solution to deposit ALD-Al2O3?BOX layers on thermally oxidized SiO2?layers, which can absorb the desorption gas from ALD-Al2O3?BOX layers.

Electron Mobility Enhancement of Extremely Thin Body In0.7Ga0.3As-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors on Si Substrates by Metal–Oxide–Semiconductor Interface Buffer Layers

Combining the split capacitance-voltage method with Hall measurements revealed the existence of interface traps within the conduction band (CB) of InGaAs in metal-oxide-semiconductor (MOS) structures with Al2O3 (or HfO2)/InGaAs interfaces. The impact of these interface traps on inversion-layer mobilities in InGaAs MOS field-effect transistors with various interface structures was investigated. We found that the interface traps (>1013 cm−2 eV−1) induce Fermi level pining at an energy level 0.21–0.35 eV above the CB minimum, which degrades the mobilities in the high inversion carrier concentration region. Furthermore, the energy levels are tunable by changing the interface structures.

Formation of III?V-on-insulator structures on Si by direct wafer bonding

We have found that a Ni-InGaAs alloy is promising material for the self-aligned metal source/drain (S/D) of InGaAs MOSFETs. The Ni-InGaAs alloy has a low sheet resistance of around 25 Ω/square and a low Schottky barrier height (SBH) for n-InGaAs. We also introduce the SBH engineering by modulating the In content in InxGa1−xAs. The value of SBH is reduced with increasing the In content with maintaining the low sheet resistance for different In contents. We propose a novel fabrication process of self-aligned metal S/D MOSFETs using Ni-InGaAs, and demonstrate the successful operation of the metal S/D InxGa1−xAs MOSFETs, for the first time. The MOSFETs have realized RSD lower by 1/5 than that in PN junction devices and the high peak mobility of 2000 and 1810 cm2/Vs in the In content of 0.7 and 0.8, respectively.

Impact of Fermi level pinning inside conduction band on electron mobility in InGaAs metal-oxide-semiconductor field-effect transistors

In this work, we report that a Ni–InP alloy can be used as a source/drain (S/D) metal for InP metal-oxide-semiconductor field-effect transistors (MOSFETs), allowing us to employ the salicidelike self-align S/D formation. Ni–InP alloys have low sheet resistance under 100 Ω/◻ and Ni can be selectively etched without etching of Ni–InP. We also demonstrate operation of the metal S/D InP MOSFETs using Ni–InP alloy. The InP MOSFETs exhibit high Ion/Ioff ratio of 106 and low subthreshold swing of 101 mV/dec.