Nobuaki Otsuka

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

A single-power supply 64 kB SRAM is fabricated in a 45 nm bulk CMOS technology. The SRAM operates at 1GHz with a 0.7 V supply using a fine-grained bitline segmentation architecture and with an asymmetrical unit-ratio 6T cell. With the asymmetrical cell, 22% cell area has been saved compared to a conventional symmetrical cell. This bulk SRAM is designed for GHz-class sub-lV operation.

A low leakage SRAM macro with replica cell biasing scheme

The growth of mobile equipment market is spurring demand for low-power SRAM macros. For mobile applications, in particular, there is a need to reduce standby current leakage while keeping memory cell data. For this purpose, several techniques have been reported. They introduce reduction of cell bias voltage in standby state, but the cell bias level is determined by Vth and supply voltage as described later. In 90nm technology and beyond, fluctuation of Vth is increasing and leakage reduction efficiency of these techniques is greatly affected. Therefore, a cell leakage reduction technique immune to process and/or environment fluctuations is required. In addition, leakage reduction in row decoder circuit is also desirable, because standby current leakage in peripheral circuits is dominated by row decoders. In order to meet these requirements, a novel cell bias control technique and a novel row decoder circuit are proposed. We fabricated a 90nm 512Kb low leakage SRAM macro.

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

We propose an IBA scheme based on a pull-out detection, which is suitable for implementing in a circuit. The scheme is implemented in a driver IC that is part of a module with an RF MEMS variable capacitor. No failures are observed over 108 cycles at 85degC, which is an accelerated charging condition.

Melt-segregate-quench programming of electrical fuse

We propose a novel electrical fuse (e-fuse) programming procedure with a melt-segregate-quench mechanism by applying a short and large current pulse. This mechanism enables a dramatic shortening of programming time. Experimental results and thermal conduction analysis are introduced for 90 nm technology.

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications

Embedded DRAMs have superior features for applications that require very high memory bandwidth, such as graphics and multimedia. To achieve high memory bandwidth, various techniques such as widening input/output pins shrinking the unit array size, and performing a read operation and a write operation concurrently have been reported. However, these embedded DRAM macros incur considerable area penalty to obtain high memory bandwidth. Among the techniques for achieving high bandwidth, the concurrent read/write operation is a very effective method in performing a read-modify-write function and a double-buffer function for the graphics applications. A pseudo-two-port embedded DRAM macro that performs concurrent read/write operations at high frequency without sacrificing cell efficiency is reported in this paper. To accomplish this, a read/write cross-point switch circuit (RWCC) and distributed steering redundancy switches (DSRS) are introduced. A 32 Mb macro is characterized via a test-chip fabricated in a 65 nm embedded DRAM process.

DFT techniques for memory macro with built-in ECC

DFT techniques to implement ECC circuitry on memory macro with no additional test cost are proposed. New methodology to design a Hamming code matrix is used to achieve whole ECC system testing with standard memory BIST and conventional test sequence. The proposed ECC techniques are implemented in a 512Kb SRAM macro and demonstrated by hardware characterization with 90nm technology.

DFT techniques for wafer-level at-speed testing of high-speed SRAMs

Design-for-test (DFT) techniques for acquiring at-speed function fail bit maps with conventional wafer test equipment are proposed. The SRAM core is operated with a high frequency clock generated by a gain-suppressed VCO which can reduce clock jitter. The data are output with a data out strobe control circuit synchronizing with an external low frequency clock. Using these techniques, the SRAM chip appears to be operating with a low frequency tester clock while the SRAM core is operated with a high frequency internal clock. Therefore, a fail bit map at high frequency operation can be obtained with conventional wafer test equipment. The at-speed test with fail bit map acquisition allows slow bit cell replacement to spare cell or chip-by-chip internal timing optimization with fuse-blowing. It results in a drastic reduction in test cost and performance yield improvement.

Bus architecture for 600-MHz 4.5-Mb DDR SRAM

A double data rate (DDR) SRAM bus architecture which can eliminate any speed penalty for doubling the I/O frequency and support single data rate (SDR) compatibility has been proposed. A method to guarantee data coherency for both DDR and SDR has also been described. With this architecture, we developed a 4.5 Mb DDR SRAM. Under the typical 2.5 V condition, a 600 MHz I/O frequency was achieved.

Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation

In this paper we propose a new metric of SRAM cell stability named static cell-flip voltage (SCFV). In order to measure SCFV, novel design-for-test (DFT) techniques with asymmetric cell-bias-voltage modulation (ACBVM) are introduced, in which the cell-data retention is measured with sweeping potential of a ground node connected to one of the cross-coupled invertors of a cell and source voltage of PMOS loads swept. It is shown that SCFV has high correlation with conventional static noise margin (SNM). The proposed techniques make it possible to directly obtain large amounts of stability data of memory cells arranged in matrix for an SRAM macro, which has been difficult with conventional SNM measurements. The measured data of 1 Kb SRAM with 65 nm technology show good correspondence with simulated results.

A 1.8 V 18 Mb DDR CMOS SRAM with power reduction techniques

In view of the remarkable progress in MPU performance, improvement in the data rate of L2 cache SRAMs is desirable to maximize system performance. As a solution, Double-Data-Rate (DDR) SRAMs, which can realize an I/O frequency of up to twice that of conventional Single-Data-Rate (SDR) SRAMs, have been reported. Increase in operation-current due to higher operation frequency causes severe power-line noise and heating. Therefore, reduction of operation-current is an important issue in designing high-speed SRAMs. In order to realize both high-frequency operation and power reduction, we propose new sense circuitry and a bit-line load scheme.