P. McFarland

A room temperature 0.1 /spl mu/m CMOS on SOI

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >

Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing

A novel method for obtaining ultra-thin, defect-free silicon on insulator (SOI) film is introduced. This technique uses epitaxial lateral overgrowth of Si (ELO) and chemical-mechanical polishing (CMP). SOI films with thicknesses of 100 nm were obtained. These films were used in fabrication and dual poly CMOS devices. The quality of the SOI film obtained is the same as that of bulk silicon, and the device characteristics are comparable with those of devices fabricated on bulk. A minimum geometry unloaded inverter ring oscillator on SOI film obtained by ELO and CMP showed a speed improvement of 3* over the bulk devices.<<ETX>>

A novel high-performance lateral bipolar on SOI

A novel lateral bipolar structure on SOI (silicon-on-insulator) is described. This device has a thin double-diffused base and a narrow emitter width, determined by the SOI thickness. It has minimal parasitic junction capacitance, as well as minimal emitter and collector resistances. Excellent device characteristics and an f/sub T/ of about 20 GHz were demonstrated.<<ETX>>

A high performance 90nm SOI technology with 0.992 /spl mu/m 2 6T-SRAM cell

This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.

High-performance devices for a 0.15- mu m CMOS technology

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.<<ETX>>

A 0.13 /spl mu/m high-performance SOI logic technology with embedded DRAM for system-on-a-chip application

Reports the successful implementation of a 0.13 /spl mu/m high-performance, silicon-on-insulator (SOI) logic technology to produce a 0.13 /spl mu/m logic-based embedded DRAM (eDRAM) on substrates composed of both bulk Si and SOI or pattern SOI. eDRAM macros are constructed in bulk regions of the wafer and high-performance logic circuits lie on SOI. Pattern SOI wafers are produced by blocking out selected regions of p-type Si wafers from the separation by implantation of oxygen (SIMOX) implant using a thick (> 1 /spl mu/m) hard mask. Test results indicate that SOI eDRAM yield and retention characteristics are comparable to bulk eDRAM. Based on ring oscillator tests, the use of 0.13 /spl mu/m SOI logic devices improves switching speeds by >20% over 0.13 /spl mu/m bulk technology at 1.2 Vdd. These results pave the way for future generations of low power SOI system-on-a-chip (SOC) applications, starting at the 0.1 /spl mu/m node.

A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar

In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the deep and shallow trench isolation processes. Next are the npn collector reach-through and anneal, CMOS well and threshold implants, gate oxidation and poly deposition. CMOS gate definition, reoxidation, and nMOS n/sup +/ implant. Electron-beam lithography is used to pattern the gate level in order to achieve a minimum gate poly width of 0.3 mu m. Next, the CMOS region is protected, while fabricating the bipolar. The annealing cycles for base and emitter during the process are compatible with the CMOS requirements. The minimum final emitter size is 0.5 mu m. CMOS ring oscillators with 50-ps delay per stage at 2.5-V supply, ECL ring oscillator delays of 48 ps at 1.2 mA, and fast loaded BiNMOS gate delays have been achieved.<<ETX>>

Trench storage capacitors for high density DRAMs

The authors have demonstrated trench capacitors with openings down to 0.25 mu m*0.25 mu m and aspect ratios as high as 40, and with a capacitance of 31 fF for 8 nm equivalent ONO (oxide/nitride/oxide) thickness. The projected trench dimensions for a 256 Mb DRAM are 0.25 mu m*0.40 mu m*4 mu m, yielding a capacitance of 30 fF when a 5 nm thick oxide dielectric is used. A capacitance of about 50 fF has been obtained using 8 nm oxide-equivalent ONO dielectric with trench dimensions of 0.25 mu m*0.4 mu m*11.5 mu m.<<ETX>>

200 mm process integration for a 0.15 /spl mu/m channel-length CMOS technology using mixed X-ray/optical lithography

An integrated 0.35 /spl mu/m CMOS technology with 0.15 /spl mu/m effective channel length (L/sub EFF/) is demonstrated in a 200 mm line. X-ray lithography is used for the critical gate level, along with conventional deep-UV and mid-UV lithography for other levels. Shallow Trench Isolation (STI) is used to achieve 0.35 /spl mu/m design rules. The NFET and PFET devices are designed for operation with a scaled power supply of 1.8 V. This technology provides 50% performance improvement relative to a 2.5 V, 0.5 /spl mu/m design rule, 0.25 /spl mu/m L/sub EFF/ high-performance CMOS technology.<<ETX>>

A simple and high-performance 130 nm SOI eDRAM technology using floating-body pass-gate transistor in trench-capacitor cell for system-on-a-chip (SoC) applications

This paper, for the first time, reports a fully-functional 130 nm trench-based eDRAM (embedded DRAM), built in unpatterned SOI. The functionality of the eDRAM is shown by the test results of: (a) 524 Kb ADM (array diagnostic monitors) macros and (b) 16 Mb product macros. The eDRAM functionality is enabled by using low-leakage floating-body array pass transistors. The support logic circuitry of the eDRAM is built using IBMs high-performance 130 nm SOI logic process technology. Wafer fixable yield as high as 67% has been obtained for 524 Kb ADMs. In addition, 16 Mb product macros were built and found to be fully fixable, exhibiting retention time on the order of 80 ms. This technology allows a simple and low-cost integration of trench-based eDRAM with high-performance SOI logic for system-on-a-chip (SoC) applications.