Michael R. Polcari

High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET.<<ETX>>

A high-performance 0.25- mu m CMOS technology. II. Technology

For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25- mu m CMOS technology are presented. Dual poly gates are fabricated using a process where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process. The TiSi/sub 2/ thickness is reduced to maintain low leakage and low contact resistance for the shallow S/D junctions. The gate level with 0.4- mu m physical length is defined using optical lithography with a contrast enhanced layer (CEL) resist system. >

A room temperature 0.1 /spl mu/m CMOS on SOI

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >

Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing

A novel method for obtaining ultra-thin, defect-free silicon on insulator (SOI) film is introduced. This technique uses epitaxial lateral overgrowth of Si (ELO) and chemical-mechanical polishing (CMP). SOI films with thicknesses of 100 nm were obtained. These films were used in fabrication and dual poly CMOS devices. The quality of the SOI film obtained is the same as that of bulk silicon, and the device characteristics are comparable with those of devices fabricated on bulk. A minimum geometry unloaded inverter ring oscillator on SOI film obtained by ELO and CMP showed a speed improvement of 3* over the bulk devices.<<ETX>>

A novel high-performance lateral bipolar on SOI

A novel lateral bipolar structure on SOI (silicon-on-insulator) is described. This device has a thin double-diffused base and a narrow emitter width, determined by the SOI thickness. It has minimal parasitic junction capacitance, as well as minimal emitter and collector resistances. Excellent device characteristics and an f/sub T/ of about 20 GHz were demonstrated.<<ETX>>

SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time

In this paper a CMOS technology that is optimum for low voltage (in the I-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effects causes a reduction of subthreshold slope at high drain bias. This lowers the high-V/sub DS/ threshold to be used, which increases the current drive without significant increase in the off-current. This technology was applied to a high performance 512 Kb SRAM. Access time of 3.5 ns at 1 V was obtained.<<ETX>>

A highly latchup-immune 1-&#181;m CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi 2

A 1-µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. Important features in this technology include thin epi substrate, retrograde n-well formed by 1-MeV ion implantation, As-P graded junctions, and self-aligned titanium disilicide. The 1-µm CMOS technology has been characterized by examining the deviceI-Vcurves, avalanche-breakdown voltages, subthreshold characteristics, short-channel effect, and sheet resistances. The devices fabricated by using the 1-MeV ion implantation and self-aligned titanium disilicide do not deviate from the conventional devices constructed with the same level of technology. With the As-P double-diffused LDD structure for the n-channel device, the avalanche-breakdown voltage is increased and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain and the polysilicon gate to 3 Ω/□ compared with 150 Ω/□ of the unsilicided counterparts. The optimized 1-µm device channel n-well CMOS resulted in a propagation delay time of 150 ps with a power dissipation of 0.3 mW. With the thin epi wafers and the retrograde n-well structure, latchup immunity is found to be greatly improved. Moreover, with the titanium disilicide formation on the source-drain, the latchup holding voltage is found to be extremely high (13 V) with the substrate grounded from the backside of the wafer. If the backside substrate is not grounded, self-aligned disilicide over n+and p+regions are found necessary to ensure high latchup immunity even in the case of thin epi on heavily doped substrate. The degradation of emitter efficiency due to the TiSi2is believed to be the dominant factor in raising the holding voltage. Detailed experimental results and discussions are presented.

Self-aligned bipolar epitaxial base n-p-n transistors by selective epitaxy emitter window (SEEW) technology

A bipolar technology which allows for very thin base formation by ultra-high vacuum/chemical vapor deposition (UHV/CVD) epitaxy and very narrow emitter width using selective epitaxial overgrowth is presented. The key step in this selective epitaxy emitter window (SEEW) process is an in situ doped epitaxial lateral overgrowth over a thin and narrow nitride/oxide pad which forms an emitter window in the sublithographic range and provides an extrinsic base contact at the same time. Advantages over conventional double-poly self-aligned technology are the very thin epitaxial base, the formation of the extrinsic base after intrinsic epitaxial base deposition resulting in a guaranteed link-up, and an emitter width in the deep submicrometer range by optical lithography. n-p-n bipolar transistors with 60-nm base width for 75 k Omega / Square Operator intrinsic base resistance and emitter widths down to 0.2 mu m with 0.07- mu m tolerance ( sigma ) have been fabricated using SEEW technology. Nearly ideal I-V characteristics have been achieved for these very narrow emitters. High-yield figures are demonstrated. The SEEW structure can provide very high current density at acceptable power level. >

A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar

In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the deep and shallow trench isolation processes. Next are the npn collector reach-through and anneal, CMOS well and threshold implants, gate oxidation and poly deposition. CMOS gate definition, reoxidation, and nMOS n/sup +/ implant. Electron-beam lithography is used to pattern the gate level in order to achieve a minimum gate poly width of 0.3 mu m. Next, the CMOS region is protected, while fabricating the bipolar. The annealing cycles for base and emitter during the process are compatible with the CMOS requirements. The minimum final emitter size is 0.5 mu m. CMOS ring oscillators with 50-ps delay per stage at 2.5-V supply, ECL ring oscillator delays of 48 ps at 1.2 mA, and fast loaded BiNMOS gate delays have been achieved.<<ETX>>