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Dive into the research topics where Paul F. Findeis is active.

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Featured researches published by Paul F. Findeis.


IEEE Transactions on Semiconductor Manufacturing | 2014

Defect Reduction by Nitrogen Purge of Wafer Carriers

Raymond Van Roijen; Pratik P. Joshi; Javier Ayala; Dane Bailey; S. Conti; William Brennan; Paul F. Findeis; Michael D. Steigerwalt

Nitrogen purge of wafer carriers is driving defect density reduction at critical process steps. We discuss several examples of defect creation related to the environment of the semiconductor wafer and how nitrogen purge of carriers improves defect density. We have applied nitrogen purge at the gate formation, SiGe epitaxy and silicide formation process steps and we report experimental split data from in line inspection and the result at electrical test. From the impact of the nitrogen purge we can draw conclusions about the nature of defect formation. The impact on volume manufacturing is demonstrated.


advanced semiconductor manufacturing conference | 2013

Defect reduction by nitrogen purge of wafer carriers

R. van Roijen; Pratik P. Joshi; D. Bailey; S. Conti; Paul F. Findeis

Nitrogen purge of wafer carriers is driving defect density reduction at critical process steps. We discuss the mechanism of defect creation and how nitrogen purge improves defect density. We report on experimental split data from in line inspection and the impact at electrical test. The effect on volume manufacturing is demonstrated.


Archive | 2010

Coaxial through-silicon via

Richard P. Volant; Mukta G. Farooq; Paul F. Findeis; Kevin S. Petrarca


Archive | 2012

Method of fabricating coaxial through-silicon via

Richard P. Volant; Mukta G. Farooq; Paul F. Findeis; Kevin S. Petrarca


Archive | 1995

Apparatus for providing solder interconnections to semiconductor and electronic packaging devices

William Brearley; Laertis Economikos; Paul F. Findeis; Kimberley A. Kelly; Bouwe W. Leenstra; Arthur G. Merryman; Eric D. Perfecto; Chandrika Prasad; James Wood; Roy Yu


Archive | 1998

Apparatus and method for use in manufacturing semiconductor devices

William Brearley; Laertis Economikos; Paul F. Findeis; Kimberley A. Kelly; Bouwe W. Leenstra; Arthur G. Merryman; Eric D. Perfecto; Chandrika Prasad; James Wood; Roy Yu


Archive | 1998

Process of reworking pin grid array chip carriers

Paul F. Findeis; John Paul Gauci; Krystyna W. Semkow; Renee L. Weisman


Archive | 1998

Plating structure for a pin grid array package

Paul F. Findeis; Kenneth R. Idler; Minkailu A. Jalloh; Thomas Albert Kelly; Emanuele F. Lopergolo


Archive | 2012

SELECTIVE ETCHING BATH METHODS

Russell H. Arndt; Paul F. Findeis; Charles J. Taft


Archive | 2012

Koaxiale Silizium-Durchkontaktierung

Mukta G. Farooq; Paul F. Findeis; Kevin S. Petrarca; Richard P. Volant

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