Stefan Pargfrieder

High-Performance Temporary Adhesives for Wafer Bonding Applications

Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking, reduced electrical resistance, and substrate flexibility. Handling of thin and ultrathin substrates however is not trivial because of their fragility and tendency to warp and fold. The thinned substrates need to be supported during the backside grinding process and through subsequent processes such as lithography, deposition, etc. Using temporary adhesives to attach the processed device wafer to a rigid carrier wafer offers an efficient solution. The key requirements for such materials are ease of application, coating uniformity with minimal thickness variation across the wafer, good adhesion to a wide variety of surfaces, thermal stability in processes such as dielectric deposition and metallization, and ease of removal to allow high throughput. An additional requirement for these materials is stability in harsh chemical environments posed by processes such as etching and electroplating. Currently available materials meet only a subset of these requirements. None of them meet the requirement of high-temperature stability combined with ease of removal. We have developed adhesives that meet a wide range of post-thinning operating temperatures. Additionally, the materials are soluble in industry-accepted safe solvents and can be spin-applied to required thicknesses and uniformity. Above all, the coatings can be removed easily without

Integration of a temporary carrier in a TSV process flow

Three-dimensional (3-D) wafer stacking technologies offer new possibilities in terms of device architecture and miniaturization [1–3]. To stack wafers, reliable through-silicon vias (TSVs) and interconnections must be processed into ultrathin wafers, and such processing is made possible by new methods for wafer handling. Of the different wafer-level bonding techniques, temporary wafer bonding adhesives can offer a variety of properties sufficient for withstanding the TSV processes: flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning processes. This paper demonstrates that, contrary to tapes and waxes currently used for temporary bonding, a new removable high-temperature adhesive meets all the requirements named above for reliable TSV processing on 8-inch active wafers. We will first describe formation of TSVs with aspect ratios of 1:1 and 2:1 into thinned wafers.

Temporary Bonding and DeBonding Enabling TSV Formation and 3D Integration for Ultra-thin Wafers

As the microelectronics industry promotes emerging and future applications, new and improved methods will be necessary to meet the manufacturing challenges associated with new products and processes. Emerging products and applications such as heterogeneous integrated chips (3D, TSV-through silicon via), radio-frequency identification tags, ever denser memory devices along with the advent of new advanced packaging technologies for a variety of products ranging from logic to memory to image sensors (CIS) require increasingly thinner substrates. While thin (<100 mum) silicon wafers exhibit increased flexibility, which in some cases is actually desired, such wafers also exhibit increased instability and fragility. The increased degree of fragility becomes even more pronounced in compound semiconductor wafers because of the mechanical properties of the constituent materials. The lack of mechanical stability and the increased fragility present a major challenge to maintaining high yield levels in volume manufacturing environments. A reliable support and handling solution is needed to overcome the above-mentioned challenges while maintaining yield levels compatible with low-cost, high-yield manufacturing processes. The solution of choice must enable safe, reliable handling of the substrates through back-thinning and backside processing while being compatible with existing (already installed) equipment lines and manufacturing processes. The most promising and most widely investigated handling solution for UltraThinreg wafers is the use of temporary bonding and debonding techniques utilizing a rigid carrier wafer to provide sufficient mechanical support. Once the product wafer is temporarily bonded to the carrier wafer, it is ready for backside processing including back-thinning, through-silicon via formation, etc. The product wafers can either be pre-processed wafers with CMOS devices as well as e.g. substrates with high-topographies like solder-balls. After completion of the backside processing steps, the product wafer can be released from the carrier wafer and proceed to final packaging processes. This paper will discuss and describe the temporary bonding process step technology, including spin/spray coating process to apply the high performance BrewerScience intermediate adhesive and the subsequent bonding step in detail. The EVG850TB (temporary bonding) equipment and the related process modules to cover this process are explained in addition. Furthermore, backside-processes (like e.g. thinning, backside metallization,.etc) which are typically applied after bonding to form e.g. TSV (through silicon vias) and the corresponding process performance are described. Once the original bonded waferstack went successfully through the backside process steps, debonding will be performed. DeBonding, in this case means, that first the thin wafer is getting debonded via thermally activated slide lift-off approach from the carrier wafer, cleaned in a single wafer cleaning chamber in order to remove the remaining adhesive residuals and than transferred to the dedicated output format. Output formats typically are either filmframe carriers, dedicated wafer cassettes, coin stack packing canisters or e.g. single wafer carriers. The carrier wafer is also getting cleaned and can then be reused again immediately for another bond-process. The EVG850DB (debonding bonding) equipment and the related process modules to cover this process are explained in detail. The paper will conclude with a discussion and comparison of silicon and glass carriers used for temporary bonding with respect to process integration and CoO.

Facilitating Ultrathin Wafer Handling for TSV Processing

Making reliable through-die interconnects for three-dimensional (3-D) wafer stacking technologies requires a reduction in wafer thickness combined with a larger wafer diameter, which in turn requires new methods for wafer handling. Of the different wafer-level bonding techniques, temporary wafer bonding adhesives are becoming increasingly important in both integrated circuit and MEMS technologies. This new generation of adhesives must possess a variety of properties to be integrated into all the required processes, including adequate flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning. The purpose of this paper is to demonstrate that, contrary to the tapes and waxes currently used for temporary bonding, a new removable high-temperature adhesive* meets all the requirements named above for reliable through-silicon via (TSV) processing on 8-inch wafers. After a presentation of the typical temporary wafer bonding process flow, the article will describe the development and the properties of the material. Secondly it will present the TSVs formed in a 70-mum thinned silicon wafer using the temporary bonding process.

3D Die-to-wafer Cu/Sn Microconnects Formed Simultaneously with an Adhesive Dielectric Bond Using Thermal Compression Bonding

The simultaneous formation of Cu/Sn microconnects and an adhesive bond during wafer level thermal compression bonding was evaluated using a 3D enabled single metal level test die and wafer. The wafer level bond process relied on locally dispensed adhesive to fix the dice to the wafer prior to bonding and to become a permanent bond during the bonding process. The die-to-wafer microconnect resistance was measured for micropad pitches of 59, 64, and 69 ¿m. The robustness of the Cu/Sn and adhesive bond was demonstrated by thinning the bonded die to 50 ¿m. Package level reliability testing of parts that were wire bonded into a thermally enhanced plastic ball grid array (PBGA) package indicates good reliability behavior and the absence of any intrinsic reliability-related issues in the microconnects.

New technologies for advanced high density 3D packaging by using TSV process

There is no question that 3D integration will be the next generation of packaging. This requires new technologies from ultra thin wafer handling to wafer to wafer bonding with 3D inter substrate connections. TSV is a process in which wafers are thinned, stacked and interconnected to significantly improve electrical performance such as signal transmission, interconnect density, reduced power consumption, form factor and manufacturing costs.

3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding

Many feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes. Todays focus lies on innovative manufacturing technologies and process integration schemes, which meet both, the economic and the technical demands. Stacking of individual chips (both chip-to-wafer and wafer-to-wafer) has the inherent advantage that different functional subsystems like logic and memory can be processed on separate wafers thereby reducing the complexity and the number of process steps greatly. The individual chips can be processed on heterogeneous materials, in different fabs and by different producers. Wafer-level integration has the advantage of higher throughput, enhanced cleanliness and the flexibility that standard fab equipment can be used for further processing. 3D integration applying chip-to-wafer bonding focuses on the yield (“good known die”) and enables to stack dies of different size e.g. several small dies on one big base die. This allows e.g. the integration of a logic device from a 300mm Si wafer with RF devices from a 150mm GaAs wafer. In this paper a higher emphasis lies on the key enabling manufacturing technologies and supported processes.

Advanced chip to wafer bonding: A flip chip to wafer bonding technology for high volume 3DIC production providing lowest cost of ownership

The shrinkage and the integration of various functionalities into electrical devices, like computers or mobile phones, lead to an ongoing need for shrinkage of the integrated semiconductor units. One possibility for manufacturing of highly integrated electrical devices is the System in Package (SiP) approach where various semiconductor chips with different functionalities are stacked and electrically connected to each other. The shrinkage affects all levels of the SiP, e.g. the transistor size, the die thickness, the height of the die stack and also the dimension and shape of interconnects between the dies. The shrinkage of the die interconnects can cause difficulties of the existing widely used joint technologies, e.g. solder bumping, because of low amount of involved solder, so that the assembly yields drops and the reliability of the interconnects lowers. The Advanced Chip to Wafer (AC2W) bonding is a two step process for stacking and bonding dies on wafers. First all dies are aligned and tacked on the wafer and in the second step all dies are bonded simultaneously permanently to the wafer. This process allows having force while bonding the dies on the wafer. In that way low solder volume interconnects can be formed on a wafer level with high assembly yield and throughput. The Cost of Ownership (CoO) connected with the throughput of the AC2W process can be an order of magnitude smaller then for comparable chip to wafer bonding processes and therefore the AC2W offers a low cost chip to wafer bonding process for high volume production. This paper will show the AC2W bonding process in detail, some issues at die joint shrinkage and a comprehensive throughput and CoO comparison between the AC2W and comparable process flows.

Throughput Enhanced Flip-Chip to Wafer Bonding: The Advanced Chip to Wafer Bonding

System-in-Package (SiP) is a semiconductor packaging and integration approach to lower costs, increase performance and decrease form factor. Because of the shrinkage of the functional structures on the chips, metal joint technology has to be used, which allow smaller pad sizes for the interconnection of the chips but as drawback needs more time and force to form the connection. Therefore the throughput at standard flip chip bonding drops dramatically. The Advanced Chip to Wafer bonding process is a two step process for bonding chips on wafer. Chips are aligned and tacked temporarily to a wafer with high throughput and then all chips are bonded in parallel permanently to the wafer with application of force, temperature and under vacuum or process gases. This process flow enables higher throughput and is therefore well suited for bonding of SiPs of high integrated chips in production.