Daniel Burgstaller

Edge Protection of Temporarily Bonded Wafers during Backgrinding

Edge chipping during backgrinding is one of the main challenges of processing temporarily bonded wafers. The edge chipping may propagate during subsequent process steps and eventually result in yield loss. We conducted a study to compare different methodologies for wafer edge protection during backgrinding, including using pre-thinned carrier wafers, large carrier wafers, edge-trimmed device wafers, and material edge modification. This paper will introduce the metrology developed to quantify edge chipping and compare the results from different protection methods.

Room temperature debonding — An enabling technology for TSV and 3D integration

3D stacked ICs (3Ds-IC) have been a hot topic for several years, but recent announcements from leading image sensor and memory manufacturers show that 3Ds-ICs finally move into high volume manufacturing. The main difference between a standard 2D wafer fab and a 3Ds-IC wafer fab is the ability to process both sides of an ultra-thin wafer and to manufacture through silicon vias (TSVs). Wide I/O DRAM is currently targeting 20μm thin wafers. The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. The silicon real estate consumed by the TSVs has to be minimized in order that the final device provides a performance advantage compared to traditional 2D devices. The only way to reduce area consumption by the TSVs is to reduce their diameter. For a given wafer thickness the reduction of TSV diameter increases the TSV aspect ratio. However, the cost and cycle time of the main TSV manufacturing process steps etching, barrier/seed layer deposition and plating increases significantly with higher aspect ratio. Thinner wafers enable smaller TSV diameters and lower TSV aspect ratios and thereby enable lower cost for TSV manufacturing [1]. The implementation of thin wafer processing in high volume memory manufacturing has brought a significant change of the requirements. In the past the early adopters of thin wafer processing in the fields of power electronics and compound semiconductors designed the backside process flow around the ability to handle and process a thin wafer. Today stacked memory applications the compatibility with standard processes at highest yield is a must. The thin wafers today usually have microbumps on both sides. To ensure high yield for thermo-compression microbump bonding the thin wafers have to fulfil wafer fab cleanliness requirements after debonding. In a nutshell the industry demands standardized processes for thin wafer handling. The revolutionary ZoneBOND® technology achieves just that — standardized and material independent processes and equipment. Temporary bonding to a rigid support carrier and debonding after backside processing have been used for thin wafer handling/processing for many years. However, so far all the debonding methods imposed severe limitations on the manufacturability. For light induced debonding the carrier had to be transparent and for solvent based debonding the carrier had to be perforated. For thermally induced debonding, “slide-off debonding” the debonding temperature had to be below the reflow temperature of the solder bumps, which limited the maximal process temperature of the adhesive. In the past the debonding method, the adhesive properties and the carrier properties were closely linked to each other. This link between debonding method, adhesive and carrier imposed severe limitations on the manufacturability. With ZoneBOND® technology the debonding process is not at all a function of the adhesive any more — debonding has become a function of the carrier. Figure 1 shows the principle of the ZoneBOND® carrier. The ZoneBOND® carrier has two zones, which differentiate by the degree of adhesion between the adhesive and the carrier. The adhesion in the center zone is reduced, whereas full adhesion is at work in the edge zone. It is important to note that the surface of the device wafer does not have to be treated at all for ZoneBOND®, which makes the technology compatible with any kind of surface passivation. This is especially important with regards to assembly after thin wafer processing. Debonding methods which rely on surface modifications of the device wafer have the inherent risk of causing adhesion problems with the underfill material during die bonding. The debonding method is compatible with bumps or pillars in the bond interface as well as on the backside of the wafer stack. No force is applied on the bumps during debonding which results in very high yields. LowTemp™ ZoneBOND® is a revolutionary breakthrough in thin wafer processing. It enables room temperature debonding, which is independent from the properties of the temporary adhesive. Thereby it enables a standardization of the debonding process and debonding equipment as it is material independent. The ZoneBOND® Open Platform for temporary adhesives enables a versatile supply chain with multiple adhesive suppliers.

Thin wafer processing - yield enhancement through integrated metrology

Thin wafer handling and processing is performed by temporary bonding to a rigid carrier wafer. The rigid carrier wafer gives mechanical support during wafer thinning and backside processing. Finally the thin wafer is debonded from the carrier wafer and attached to a dicing tape on film frame. While this technology has been demonstrated for a couple of years now in pilot line and small volume, it is an entirely different story to transfer such a technology to high volume manufacturing (HVM).

Recent progress in thin wafer processing

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D IC. The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. The silicon real estate consumed by the TSVs has to be minimized in order that the final device provides a performance advantage compared to traditional 2D devices. The only way to reduce area consumption by the TSVs is to reduce their diameter. For a given wafer thickness the reduction of TSV diameter increases the TSV aspect ratio. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. While the majority of the device manufacturing steps on the front side of the wafer will be completed with the wafer still at full thickness, it will be temporarily mounted onto a carrier before thinning and processing of the features on its backside. Once the wafer reaches the temporary bonding step, it already represents a significant value, as it has already gone through numerous processing steps. For this reason, inspection of wafers prior to non-reworkable process steps is of great interest. Within the context of Temporary Bonding this consideration calls for inline metrology that allows for detection of excursions of the temporary bonding process in terms of adhesive thickness, thickness uniformity as well as bonding voids prior to thinning of the product wafer. This paper introduces a novel metrology solution capable of detecting all quality relevant parameters of temporarily bonded stacks in a single measurement cycle using an Infrared (IR) based measurement principle. Thanks to the IR based measurement principle, the metrology solution is compatible with both silicon and glass carriers. The system design has been developed with the inline metrology task in mind. This has led to a unique system design concept that enables scanning of wafers at a throughput rate sufficient to enable 100% inspection of all bonded wafers inline in the Temporary Bonding system. Both, current generation temporary bonding system throughputs and future high volume production system throughputs as required by the industry for cost effective manufacturing of 3D stacked devices were taken into account as basic specifications for the newly developed metrology solution. Sophisticated software algorithms allow for making pass/ fail decisions for the bonded stacks and triggering further inspection, processing and / or rework. Actual metrology results achieved with this novel system will be presented and discussed. In terms of adhesive total thickness variation (TTV) of bonded wafers, currently achieved performance values for postbond TTV will be reviewed in light of roadmaps as required by high volume production customers.

Low temperature packaging of BioMEMS and Lab-on-chip devices

BioMEMS in general and specifically Lab-on-chip devices for point-of-care diagnostics offer tremendous potential to improve the health care situation in developed and developing countries. Lab-on-chip devices enable the widespread and fast detection of infectious diseases as well as the continuous diagnosis and customized treatment of chronic diseases like diabetes. Implementing microfluidics and micromanufacturing enables massive parallelization of the diagnosis thereby allowing multiple different tests at once.

Temporary-bonding and LowTemp® debonding technology for various applications

A standard TB/DB technology capable of wide-range of adhesives is strongly required for various TB/DB applications. Maximum temperature of backside process was investigated for 5 kinds of adhesives. ZoneBOND™ technology has been demonstrated to have much flexibility in adhesives, resulting applicable to various applications.