Paul Zimmerman

High-Performance Deep Submicron Ge pMOSFETs With Halo Implants

Ge pMOSFETs with HfO2 gate dielectric and gate lengths down to 125 nm are fabricated in a Si-like process. Long-channel hole mobilities exceed the universal curve for Si by more than 2.5 times for vertical effective fields as large as 1 MV/cm. The mobility enhancement is found to be relevant at submicron gate lengths, and a drive current of 1034 muA/mum is achieved for L=125 nm at VG-VT=VD=-1.5 V. The introduction of halo implants allows significantly improved control of short-channel effects, with approximately three orders of magnitude reduction in source junction off-current. VT rolloff and drain-induced barrier lowering are reduced from 207 mV and 230 mV/V to 36 mV and 54 mV/V, respectively, for the highest n-well dose investigated. Four key logic benchmarking metrics are used to demonstrate that Ge is able to outperform Si down to the shortest investigated gate length, with an almost twofold improvement in intrinsic gate delay. ION=722 muA/mum is demonstrated for IOFF=11 nA/mum at a power supply voltage of -1.5 V, when evaluating from the source.

Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

We demonstrate for the first time the performance of aggressively scaled triple gate devices with a MOCVD TiN/HfO gate stack. The transistors have physical gate lengths down to 40 nm, and 60 nm tall and 10 nm wide fins. We show that MOCVD TiN can be used to successfully set the threshold voltage of both nMOS and pMOS devices in the range of |0.4-0.5| V. Devices with excellent Ion/Ioff behavior were obtained with reduced gate leakage values.

Effective work function modulation by controlled dielectric monolayer deposition

It is shown that the interface between gate dielectric and metal electrode critically determines the effective work function and hence metal oxide semiconductor field effect transistor threshold voltage. Electrostatic potential at the interface is perturbed by a polarization layer and this can be engineered at a monolayer level. It is demonstrated that the interface polarization layer can be modified by carefully depositing both dielectric and metal gate materials followed by a high temperature treatment offering a route to work function control.

Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions

For the first time, scaled PMOS MUGFET devices with TiCN/HfO2 gate stack is doped with specific pulsed plasma doping processes. This paper first highlights the key benefit brought by conformal source/drain extensions, demonstrates how pulsed plasma doping process can be tuned to conformal dope very dense fin structures and finally shows that high performance (+24% vs. ion implant reference) multi-gate pMOS device (720 muA/mum @ Ioff 20nA/mum, at Vds = -1.2V) is achieved with extensions formed by optimized PLAD process

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (i.e., workfunction close to midgap), several parasitic leakage mechanisms that impact the off-state current become dominant. We provide a detailed characterization of these mechanisms as well as design guidelines for eliminating them by careful junction dopant placement and S/D silicide engineering in order to achieve high Ion/Ioff ratios. Up to 20times GIDL reduction is achieved with minimum drive loss with asymmetric extensions. Using selective epitaxy on S/D, suppression of parasitic Schottky effects is also demonstrated resulting in a Ioff reduction of 10000times

Metallorganic Chemical Vapor Deposition of Dysprosium Scandate High-k Layers Using mmp-Type Precursors

Rare-earth scandate materials have been identified as candidates for gate dielectrics in metal oxide semiconductor transistors because of their high thermal stability against crystallization in combination with a high-dielectric constant. In this study, tris(1-methoxy-2-methyl-2-propoxy)dysprosium [Dy(mmp) 3 ] and Sc(mmp) 3 are evaluated as metallorganic chemical vapor deposition precursors for deposition of Dy x Sc y O z on silicon at moderate temperatures (450-600°C). These temperatures allow easy integration into a standard transistor flow. The layers are uniform with a close to bulk density and smooth top surface. Electrical characterization measurements shows a gate leakage current of 1.8 X 10 -5 A/cm 2 at 4.5 V for an equivalent oxide thickness of 2.0 nm. Limited hysteresis (9 mV) and frequency dispersion (3% difference in accumulation capacitance between 10 and 250 kHz) was observed.

Integration challenges for multi-gate devices

The FinFET transistor is the most widely studied and known multi-gate architecture that has the potential to be scaled to beyond the 45 nm technology node. In this paper a number of integration issues have been addressed. In first section the patterning challenges have been discussed. Due to the particular layout of the FinFET devices a variation in fin width is seen due to the rounding of the fin opening. This problem can be addressed by looking at alternative litho settings and OPC. Next to that topography plays an important in patterning the gate. It is seen that the optimization of the different OE times is key in achieving a controlled gate profile without poly residues. Techniques like poly etch-back can be used to alleviate the topography issues as much as possible. Threshold voltage tuning with implantation is extremely difficult for narrow fin devices. Workfunction tuning by either deposited metal gate or full silicidation is seen as a more viable solution. The extensions and deep source/drain areas need to be as conformal as possible in order to avoid the dominance of the top channel over the sidewalls. However, conventional implantation techniques are unsuitable and alternative implantation techniques need to be investigated. Next to that, when high density is needed, the fin spacing will limit the allowed tilt angle due to implant shadowing. The sidewall crystal orientation is different from that of the top channel and this will impact the mobility of holes and electrons in a different way. Rotation of the fins over 45 degrees, the use of strained layers and strained SiGe source/drain have been briefly discussed as possible solutions to tackle this problem. Finally, the impact of the fin width on R/sub SD/ has been shown. Elevated source/drain has been brought forward as a solution to this problem.

Silicon Orientation Effects in the Atomic Layer Deposition of Hafnium Oxide

The continuous downscaling of complementary metal oxide semiconductor devices demands the introduction of dielectric layers with a high permittivity K. Three-dimensional (3D) transistor structures, such as FinFET devices, require excellent step coverage by the high-K material as provided by atomic layer deposition (ALD). In addition, because of the 3D structure, surfaces with different crystallographic orientation need to be covered. Because the initial HfO 2 deposition using ALD HfCl 4 /H 2 O is governed by the OH surface density, we investigated its dependence on the crystallographic orientation of the silicon substrate. For oxidations in O 3 /H 2 O, a (110) orientated substrate oxidizes faster than silicon (100) up to a thickness of ∼0.7 nm as measured by X-ray photoelectron spectroscopy. Also, irrespective of the substrate orientation, the HfO 2 deposition is found to increase with increasing SiO 2 thickness and thus OH coverage of the surface. This implies that, for oxide thicknesses below0.7 nm, the oxidation of silicon (100) results in a thinner oxide and, hence, less HfO 2 deposition in comparison to silicon (110). However, these differences are marginal after implementation in transistor devices as is shown by their capacitance and mobility. As a result, for FinFET applications, a conformally deposited HfO 2 layer will be independent of the crystallographic substrate orientation.

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate devices with narrow fins. This makes selective epitaxial growth of Si in the S/D regions, the enabling process for multiple gate CMOS technologies. In this paper, we endeavor to integrate a low temperature selective epitaxial growth process and a low temperature NiSi process to form low resistance S/D contacts. Our experimental results show 34% and 11% improvement in parasitic S/D resistance of N-and P-channel multiple gate FETs with less than 20 nm wide fins respectively.

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

Effective mobility measurements have been made at 4.2 K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.