M. Goodwin

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.

Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification

A model for NBTI is proposed based on disorder-controlled diffusion and drift in amorphous dielectrics. Experimental data on finFETs confirm all major predictions of the model: temperature dependence of the NBTI exponent, non-Arrhenius behavior of NBTI, log(t) and electric field dependencies of recovery. Experimental challenges with determining NBTI parameters are also highlighted.

Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

We demonstrate for the first time the performance of aggressively scaled triple gate devices with a MOCVD TiN/HfO gate stack. The transistors have physical gate lengths down to 40 nm, and 60 nm tall and 10 nm wide fins. We show that MOCVD TiN can be used to successfully set the threshold voltage of both nMOS and pMOS devices in the range of |0.4-0.5| V. Devices with excellent Ion/Ioff behavior were obtained with reduced gate leakage values.

Performance improvement of tall triple gate devices with strained SiN layers

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.

Temperature dependence of the negative bias temperature instability in the framework of dispersive transport

Negative bias temperature instability (NBTI) is studied in multiple-gate field-effect transistors with an ultrathin gate oxide. It is observed that the threshold voltage shift in these devices follows a power-law function of time, with the exponent depending linearly on temperature. An analytic model is proposed that explains this temperature dependence by dispersive diffusion of hydrogen in the bulk of the gate oxide. Based on both the experimental data and the model, it is concluded that NBTI is an inherently non-Arrhenius process.

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

This paper shows, for the first time, the successful introduction of recessed, strained Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions of pMOS MuGFET devices, improving the on-state current of these devices by 25%, at a fixed off-state condition. The improvement is shown to be a combined effect of compressive stress introduced along the channel, and of a reduced series resistance.

Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions

For the first time, scaled PMOS MUGFET devices with TiCN/HfO2 gate stack is doped with specific pulsed plasma doping processes. This paper first highlights the key benefit brought by conformal source/drain extensions, demonstrates how pulsed plasma doping process can be tuned to conformal dope very dense fin structures and finally shows that high performance (+24% vs. ion implant reference) multi-gate pMOS device (720 muA/mum @ Ioff 20nA/mum, at Vds = -1.2V) is achieved with extensions formed by optimized PLAD process

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (i.e., workfunction close to midgap), several parasitic leakage mechanisms that impact the off-state current become dominant. We provide a detailed characterization of these mechanisms as well as design guidelines for eliminating them by careful junction dopant placement and S/D silicide engineering in order to achieve high Ion/Ioff ratios. Up to 20times GIDL reduction is achieved with minimum drive loss with asymmetric extensions. Using selective epitaxy on S/D, suppression of parasitic Schottky effects is also demonstrated resulting in a Ioff reduction of 10000times

On the scalability of source/drain current enhancement in thin film sSOI

This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

We demonstrate a novel CMP-less dual hard mask scheme for the integration of fully silicided gates in FinFETs by simultaneous silicidation of the gate, source and the drain. V/sub T/ of 0.18V and -0.2V are demonstrated for 50nm gate length NFET and PFET respectively. Competitive I/sub on/-I/sub off/ of 960uA/um-140nA/um for NFET and 620uA/um-100nA/um for PFET were obtained at V/sub D/=l .3V for an EOT of 1.8nm.