Ken Rim

SOI CMOS Technology with 360GHz f T NFET, 260GHz f T PFET, and Record Circuit Performance for Millimeter-Wave Digital and Analog System-on-Chip Applications

We present record-performance RF devices and circuits for an SOI CMOS technology, at 35 nm Lpoly. Critical RF/analog figure of merits in FET such as current gain cut-off frequency (fT), 1/f noise, and high-frequency noise figure at various bias and temperature conditions are measured and modeled to enable high-performance circuit design. Measurement results show peak fTs of 340 GHz and 240 GHz for 35 nm Lpoly NFET and PFET, respectively. At sub-35 nm Lpoly, 360 GHz fT NFET and 260 GHz fT PFET are demonstrated. High-Q, high-density vertical native capacitors (VNCAPs) and on-chip inductors are integrated. RF-operable ring oscillator (RFRO) demonstrates a 3.58 psec delay and a SSB phase noise of -107 dBc/Hz at 1 MHz offset. LC-tank VCO operates at 70 GHz with 9.5% tuning range. The maximum operating frequency of a static CML divider is 93 GHz while dissipating 52.4 mW.

Strained Si surface channel MOSFETs for high-performance CMOS technology

Biaxial tension enhances in-plane transport of both electrons and holes in silicon, and can improve the current drive of CMOS devices independent of geometric scaling and electrostatic design. Device performance enhancements and issues to be addressed before the realization of strained Si CMOS technology are discussed.

An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS

CMOS VCOs have been implemented for mm-wave applications [1–7], however, as the required channel bandwidth for these applications increases, wide-range VCO tuning is becoming more challenging. Even without taking into account the process variability in nanometer CMOS, a single VCO hardly achieves requirements for a mm-wave band and phase-noise performance, and it suffers from the steep VCO loop gain. Taking advantage of parallelism, using an array of VCOs is emerging as an alternative technique to implement a wide-band VCO (Fig. 16.3.1). While nanometer CMOS technology is becoming the next generation RF and mm-wave platform (because of high-speed performance due to technology scaling and and SoC integration capability), costly technology developments and mask sets further promote the use of array-based VCOs to expedite yield learning and circuit-development cycle. However, a VCO array requires more circuit area. Conventional designs are not scalable because of their size, cost, and complications for signal delivery. Technology scaling for mm-wave SoC is driven by the high-speed device performance while digital systems benefit from increased device density. In mm-wave applications, passive components, especially inductors, are responsible for area budget, since their area is not scaled with the technology. Taking advantage of nanometer FETs, the presented complementary LC-VCO is attractive for VCO arrays. It uses an LC-tank and its area is minimal and highly scalable. The use of state-of-the-art nanometer CMOS technology is essential to retain high-speed design margin for mm-wave circuits and provisions are required to make the complementary LC-VCO more scalable and manufacturable against the process variability and technology uncertainty. After all, the VCO array provides mm-wave-component performance-variability metrics as a feedback to the technology foundry. Such components are difficult and expensive to characterize and the required on-chip probe pads waste silicon area.

High-performance silicon-germanium technology

This paper will focus on the various and ubiquitous uses of silicon-germanium (SiGe) in high-performance silicon-based semiconductor technology. SiGe can now qualify as a mature technology - it is almost 20 years since the first SiGe HBT work. It is 10 years since the qualification of SiGe as a manufacturable silicon technology in a high-volume silicon fabricator

Improved effective switching current (I EFF + ) and capacitance methodology for CMOS circuit performance prediction and model-to-hardware correlation

New effective drive current I_EFF ⁺ methodologies are demonstrated in this paper to address predictability of circuit performance across wide Vt range and accuracy of effective resistance R_EFF prediction-to-hardware correlation. Two separate I_EFF definitions are adopted for delay performance prediction (I_EFF = [I_H + I_L]/2), and ring AC/DC prediction-tohardware correlation analysis (I_EFF ⁺ = [1.15I_H + I_L + G_DS,LIN* VDD/80]/2). I_EFF ⁺ results in perfect matching in ring AC and DC effective resistance across SOI and bulk technologies. I_EFF combined with Vt-dependent effective switching capacitance (C_{EFF_Delay}) also leads to good match between predicted performance and spice simulation across wide Vt range using simple CMOS device parameters.

Reverse Temperature Dependence of Circuit Performance in High-

The temperature dependence of ring-oscillator delay of high-kappa /metal-gate (HKMG) and poly-Si/SiON technologies are analyzed. HKMG gate stacks drive significantly stronger threshold temperature dependence over poly-Si/SiON. This effect, together with the reduced mobility temperature sensitivity, result in higher drive current at elevated temperature for HKMG devices. This is in contrast to poly-Si/SiON technology where the low-driven current performance-limiting corner is typically at high temperature.

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The temperature dependence of device performance is a critical factor that determines overall product power-performance. We show HKMG gate stacks drive significantly higher threshold temperature dependence over poly-Si/SiON. We further show that in SOI, the work-function engineering enabled by HKMG integration schemes can result in even higher Vt temperature sensitivity attributed to differences in floating body behavior. These combined effects, together with observed reduced mobility temperature sensitivity, result in higher drive current at elevated temperature. This is in contrast to poly-Si/SiON technologies where the low driven current, performance limiting corner is typically at high temperature.

/Metal-Gate Technology

A systematic method is proposed to address modeling challenges in accurate chip level leakage prediction, namely a precise total leakage width count method, a simple model to quantify leakage uplift caused by systematic across-chip variation, and a consistent model to capture 3-sigma leakage and leakage spread at fixed performance.

On the difference of temperature dependence of metal gate and poly gate SOI MOSFET threshold voltages

Parameters for a generalized mobility model are extracted from hardware measurements of strained silicon NMOS devices. Only the phone limited mobility parameter was shown to vary with amount of strain in the silicon.Using results of the mobility model fitting, simulations of strained and unstrained silicon devices were performed. These simulations indicated that strained silicon devices should have improved short channel control as well as yield a minimum of 50% improvement in on current.

Accurate chip leakage prediction: Challenges and solutions

Two FinFET fabrication processes are compared with simulation: the conventional fin-first process and the novel fin-last process. With the fin-last process, more longitudinal strain can be incorporated into the channel from source and drain SiGe stressor than fin-first. pFET mobility advantage is 15% at fully-strained condition and with silicon recess. Maintaining vertical junction uniformity is the main challenge for fin-last. However, its impact on parasitic resistance and capacitances are small. Vertical junction non-uniformity is improved with source and drain recess and doping optimization.