Piyas Samanta

Electrical stress-induced charge carrier generation/trapping related degradation of HfAlO/SiO2 and HfO2/SiO2 gate dielectric stacks

A comparative study on charge carrier generation/trapping and related degradation in HfAlO/SiO2 and HfO2/SiO2 stacks with identical equivalent-oxide-thickness (EOT) is presented during constant gate voltage stress of n-type metal-oxide-semiconductor capacitors. Compared to HfO2 devices, HfAlO devices with an equal EOT show better performances in memory and logic applications. On the contrary, at a given stress voltage, the threshold voltage degradation and stress-induced leakage current degradation in HfAlO samples are higher, indicating shorter device lifetime compared to the HfO2 samples of same EOT. In addition, the mechanism of charge trapping in the oxide as well as at the Si/SiO2 interface of both capacitors is investigated and a model is proposed. A similar generation kinetics was observed for stress-induced oxide trapped positive charges and interface states in either of the devices.

Direct tunneling stress-induced leakage current in ultrathin HfO2∕SiO2 gate dielectric stacks

The conduction mechanism(s) and behavior of direct tunneling stress-induced leakage current (SILC) through ultrathin hafnium oxide (HfO2)/silicon dioxide (SiO2) dual layer gate stack in metal-oxide-semiconductor (MOS) devices have been experimentally investigated in-depth. Both transient and steady-state SILCs have been studied after constant voltage stress (CVS) and constant current stress (CCS) in n-MOS capacitors with negative bias on the tantalum nitride (TaN) gate. The present report clearly indicates that the observed steady-state SILC is due to assisted tunneling via both monoenergetic trapped positive charges and neutral electron traps generated in the HfO2 layer during either CVS or CCS. SILC measured immediately after stress decays slowly due to tunnel detrapping of stress-induced trapped holes in the HfO2 layer. Furthermore, the mechanisms for stress-induced charge carrier generation/trapping and trap creation in the dielectric have been discussed. Our analysis also shows that CVS degrades the ...

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

Abstract We compare charge carrier generation/trapping related degradation in control oxide (SiO 2 ) and HfO 2 /SiO 2 stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained Si O Si bonds in either of the devices. We demonstrate that compared to SiO 2 devices, HfO 2 devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO 2 devices at a given operating voltage.

Charge Trapping Related Degradation of Thin HfAlO ∕ SiO2 Gate Dielectric Stack during Constant-Voltage Stress

Charge carrier generation/trapping and the related degradation of a thin HfAlO/SiO 2 stack in n-type metal-oxide-semiconductor capacitors have been investigated under constant gate voltage stress. The results show that dielectric degradation is a composite effect of neutral trap creation, surface state generation at the Si/SiO 2 interface, and positive charge trapping in the bulk. The neutral traps created during stress are homogeneously distributed across the oxide following Poissons random statistics. A significant amount of border-trapped charges was observed in both as-deposited and poststressed devices. The kinetics of generation of both oxide-trapped positive charges and interface trapped charges are found to be similar. Both these defects are possibly created by the hydrogen-related species. We demonstrate that compared to HfO 2 devices, HfAlO devices with an equal equivalent oxide thickness (EOT) show better performances in memory and logic applications. On the contrary, at a given stress voltage, the threshold voltage degradation ΔV T and stress-induced leakage current degradation in HfAlO samples are larger, indicating a shorter device lifetime compared to the HfO 2 samples of the same EOT.

Interface trap generation and recovery mechanisms during and after positive bias stress in metal-oxide-semiconductor structures

Interface trap (Nit) generation and their partial recovery during and after cessation of the positive bias-temperature stress (PBTS) in n-type metal-oxide-semiconductor capacitors have been investigated. The analysis of experimental results indicates that Nit creation is caused by the depassivation of Si3≡Si-H bonds at the Si/SiO2 interface by the atomic neutral hydrogen (H0) cracked via electron impact at or near gate/oxide interface during electron injection from the substrate. Nit recovery after interruption of the stress is due to back diffusion of H2 species toward the Si/SiO2 interface and repassivation of Si3≡Si• dangling bonds. We propose that in absence of holes, a modified one dimensional reaction-diffusion (R-D) model following three step degradation sequences can qualitatively explain the generation and the recovery of Nit during and after PBTS.

On the electrical stress-induced oxide-trapped charges in thin HfO2∕SiO2 gate dielectric stack

Oxide charge buildup and its generation kinetics during constant voltage stress in TaN∕HfO2∕SiO2∕p-Si structures have been experimentally investigated. From the oxide charge relaxation experiments, nature and energy location of the as-fabricated intrinsic hole traps in the gate stack have also been determined. Our measurement results indicate that the dispersive proton transport through the interfacial SiO2 contributes larger than hole trapping in positive charge buildup in the stack. From the bias temperature stress measurement results in both control oxide and HfO2∕SiO2 stacks, we have identified overcoordinated [Si2=OH]+ centers as the proton-induced defects located in the interfacial SiO2 layer of the stack. Finally, an empirical equation is proposed to explain the stress-induced oxide positive charge buildup.

Leakage current conduction, hole injection, and time-dependent dielectric breakdown of n-4H-SiC MOS capacitors during positive bias temperature stress

The conduction mechanism(s) of gate leakage current JG through thermally grown silicon dioxide (SiO2) films on the silicon (Si) face of n-type 4H-silicon carbide (4H-SiC) has been studied in detail under positive gate bias. It was observed that at an oxide field above 5 MV/cm, the leakage current measured up to 303 °C can be explained by Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps located at ≈2.5 eV below the SiO2 conduction band. However, the PF emission current IPF dominates the FN electron tunneling current IFN at oxide electric fields Eox between 5 and 10 MV/cm and in the temperature ranging from 31 to 303 °C. In addition, we have presented a comprehensive analysis of injection of holes and their subsequent trapping into as-grown oxide traps eventually leading to time-dependent dielectric breakdown during electron injection under positive bias temperature stress (PBTS) in n-4H-SiC metal-...

Experimental evidence of two conduction mechanisms for direct tunnelling stress-induced leakage current through ultrathin silicon dioxide gate dielectrics

A comprehensive analysis of the stress-induced leakage current (SILC) through thermally grown ultrathin silicon dioxide (SiO2) films has been presented based on experimental observations. Stressing and sensing measurements are done in tantalum nitride (TaN) gate metal-oxide-silicon (MOS) capacitors at negative gate bias in the direct tunnelling (DT) regime. Both transient and steady-state DT SILCs have been studied in oxides with thicknesses between 1.7 and 2.3 nm. On the premise of charge carrier generation/trapping characteristics, our experimental results give a better physical insight into the conduction mechanism of SILC through ultrathin SiO2 films stressed in the DT regime. We propose a physical model of SILC conduction on the basis of experimental evidence of two distinctly different conduction paths for DT SILC. Monitoring SILC behaviour, the monoenergetic nature of stress-induced neutral traps and hydrogen-induced defects in the oxide is established. Furthermore, our analysis shows that constant voltage stress degrades the device performance more severely than constant current stress.

Effects of gate material on Fowler-Nordheim stress induced thin silicon dioxide degradation under negative gate bias

An exhaustive theoretical investigation on the role of gate material as well as commonly used metal deposition processes [viz., electron beam (e-beam) evaporation and thermal evaporation] on high-field stress-induced dielectric breakdown and∕or degradation of identically thick (8–10nm) thermally grown silicon dioxide (SiO2) films used in memory devices has been reported. Gate materials studied here are n+-polycrystalline silicon (polySi) and aluminum (Al) with n-channel metal-oxide-semiconductor field effect transistor structures. Results will be shown here during constant current and constant field Fowler-Nordheim (FN) tunnel injection from the gate into SiO2. Our theoretical results establish that Al-gated structures exhibit poorer dielectric integrity compared to polySi-gated structures under both types of FN stressing technique. Furthermore, compared to thermally deposited Al-gated samples, e-beam evaporated Al-gated samples show slightly higher gate oxide deterioration in either mode of FN stressing ...

Electron detrapping in thin hafnium silicate and nitrided hafnium silicate gate dielectric stacks

The kinetics of zero-field and field-induced detrapping of electrons trapped in HfSixOy and HfSiON after positive bias stress on n+-polycrystalline silicon (polySi) gate of n-type metal-oxide-semiconductor (nMOS) capacitors are experimentally investigated. The self detrapping follows a simple logarithmic relation with time while field-induced detrapping upon reversing the stress voltage obeys a simple first-order exponential decay suggesting mono energetic shallow traps associated with tunnel emission of trapped electrons. Finally, our investigation raises questions about the validity of the widely used distributed capture cross section model of electron traps to explain the threshold voltage instability in MOS devices with hafnium silicate gate stacks.