Qi Lin

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric

A new adaptation strategy of I/O link equalizers is presented based on minimizing the bit error rate (BER) as the objective function to maximize the receiver voltage margin. The adaptation strategy is verified in a 90-nm test chip on both the transmitter finite-impulse response filter (Tx-FIR) and the receiver decision-feedback equalizer (Rx-DFE). The performance is compared with the commonly used sign-sign least mean square (SS-LMS) adaptation and demonstrates significant improvements especially in the case of the Tx-FIR. This paper also demonstrates that in a highly attenuating system that contains both a Tx-FIR and Rx-DFE, using a Tx-FIR subject to peak output power constraint to compensate pre-cursor ISI is worse than solely using an Rx-DFE. The adaptation strategy is further applied to adapt the sampling phase of the clock-and-data recovery loop (CDR). The technique enables near-optimal BER performance by substantially reducing the pre-cursor ISI and requires almost no additional hardware compared to SS-LMS adaptation.

Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.

Precursor ISI Reduction in High-Speed I/O

To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the interaction between equalization adaptation and clock-data recovery (CDR), coupled with transmitter peak-power constraint. To minimize the impact of precursor ISI on the bit-error-rate (BER), we propose a new method of adapting CDR phase for maximum voltage margin.

Accurate System Voltage and Timing Margin Simulation in CDR Based High Speed Designs

Accurate analysis of system timing and voltage margin at a target bit error rate across process, voltage, and temperature variations is required for high volume production of high speed systems. This in turn requires a statistical simulation framework to model the effectiveness of advanced signaling techniques such as transmitter equalization and receiver decision feedback. Furthermore, for data and telecommunication networking serial links, one must also carefully model the clock-data recovery circuits (CDR) and understand their impact on system voltage and timing margin. In this paper, we first present a stochastic simulation framework and describe a modeling methodology for CDR circuits. We then compare the simulation results based on CDR modeling to a simple method, which uses a quadrature sampling based timing recovery model. Finally, we correlate the simulation results to lab measurements to validate the proposed approach

A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces

A 5Gb/s signaling system was designed and fabricated in TSMCs 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency transmit clock jitter and supports rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution via embedded clocking with superposition of clock in the common-mode was also explored.