R. J. P. Lander

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations

This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large vertical compressive strain is observed in metal gate FinFETs, and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFET lateral interfaces with respect to (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of stress components in the fin width, height, and length directions on the mobility of both n- and p-type FinFETs and to identify optimal stress configurations. Finally, self-consistent Monte Carlo simulations are used to investigate how the most favorable stress configurations can improve the on current of nanoscale MOSFETs.

Low frequency noise measurements of p-channel Si/sub 1-x/Ge/sub x/ MOSFET's

In this brief, we report an investigation of the low frequency noise in p-channel SiGe MOSFETs. At low gate bias the noise spectrum consists of several trap related generation-recombination (g-r) noise components. At higher gate bias, the noise spectrum is dominated by 1/f noise. The 1/f noise is attributed to a fluctuation in the number of free carriers and the effective slow state trap density at the Fermi energy calculated.

Matching Performance of FinFET Devices With Fin Widths Down to 10 nm

In this letter, the matching performances of FinFET devices with high-k dielectric, metal gates, and fin widths down to 10 nm are experimentally analyzed. The stochastic variation of threshold voltage and current factor is examined for both p- and n-type FinFETs. An improvement of the matching performance is expected compared to conventional planar bulk devices since the fins are undoped. The impact of line edge roughness and charge density in the high-k dielectric is evaluated in order to understand which physical parameter fluctuation is dominant on the measured matching parameters.

First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in beta-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs

This study combines direct measurements of channel strain, electrical mobility measurements and a rigorous modeling approach to provide insight about the strain induced mobility enhancement in FinFETs and guidelines for the device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel technique. A large vertical compressive strain is observed in FinFETs and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFETs lateral interfaces w.r.t. (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of the fin-width, fin-height and fin-length stress components on n- and p-FinFETs mobility and to identify optimal stress configurations.

FinFET Mismatch in Subthreshold Region: Theory and Experiments

In this paper, we study the drain-current mismatch of FinFETs in subthreshold, from both modeling and experimental point of view. We propose a simple model that takes into account the effect of threshold voltage and subthreshold swing fluctuations and their correlation. For long-channel devices (longer than a critical length LC), characterized by a subthreshold swing close to the ideal value, the overall current mismatch is dominated by threshold voltage fluctuations and, therefore, is gate voltage independent. The subthreshold swing fluctuations give a negligible effect on the drain-current mismatch and are uncorrelated with the threshold voltage fluctuations. For short-channel devices (shorter than a critical length LC), characterized by a strong dependence of subthreshold swing on the channel length, the overall current mismatch presents an additional relevant contribution associated with the subthreshold swing fluctuations. This component depends on the gate voltage overdrive and is ascribed to the gate line edge roughness, resulting in a partial correlation between threshold voltage and subthreshold swing fluctuations.

Improved fin width scaling in fully-depleted FinFETs by source-drain implant optimization

Scaling the fin width in fully-depleted FinFETs can improve short channel effect control, but may be accompanied by a on-state drive current degradation. Ion implantation is a leading candidate as the means to introduce dopants into the silicon, but is often accompanied by amorphization when highly doped source-drain regions are formed. Thin-body silicon recrystallization after amorphization is not as straight-forward as bulk silicon. Crystalline integrity is worse as the fin width is scaled, thereby reducing dopant activation and increasing access resistance. In this work we demonstrate that non-amorphizing implant approaches can overcome drive degradation down to 10 nm wide fins in pMOS FinFETs.

Atomistic modeling of impurity ion implantation in ultra-thin-body Si devices

Source/drain formation in ultra-thin body devices by conventional ion implantation is analyzed using atomistic simulation. Dopant retention is dramatically reduced by backscattering for low-energy and low-tilt angles, and by transmission for high angles. For the first time, molecular dynamics and kinetic Monte Carlo simulations, encompassing the entire Si body, are applied in order to predict damage during implant and subsequent recovery during anneal. These show that amorphization should be avoided as recrystallization in ultra-thin-body Si leads to twin boundary defects and poly-crystalline Si formation, despite the presence of a mono-crystalline Si seed. Rapid dissolution of end-of range defects in thin-body Si, caused by surface proximity, does not significantly reduce diffusion lengths. The conclusions of the atomistic modeling are verified by a novel characterization methodology and electrical analysis.

On the role of Coulomb scattering in hafnium-silicate gated silicon n and p-channel metal-oxide-semiconductor-field-effect-transistors

In this work, the impact of the local and remote Coulomb scattering mechanisms on electron and hole mobility are investigated. The effective mobilities in quasi-planar finFETs with TiN/Hf0.4Si0.6O/SiO2 gate stacks have been measured at 300 K and 4 K. At 300 K, electron mobility is degraded below that of bulk MOSFETs in the literature, whereas hole mobility is comparable. The 4 K electron and hole mobilities have been modeled in terms of ionized impurity, local Coulomb, remote Coulomb and local roughness scattering. An existing model for remote Coulomb scattering from a polycrystalline silicon gate has been adapted to model remote Coulomb scattering from a high-κ/SiO2 gate stack. Subsequently, remote charge densities of 8 × 1012 cm−2 at the Hf0.4Si0.6O/SiO2 interface were extracted and shown to be the dominant Coulomb scattering mechanism for both electron and hole mobilities at 4 K. Finally, a Monte Carlo simulation showed remote Coulomb scattering was responsible for the degraded 300 K electron mobility.