Seiichi Aritome

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current. >

Fast and accurate programming method for multi-level NAND EEPROMs

For the replacement of conventional hard disks by NAND EEPROMs, a very high density and a high programming speed are required. An increased density can be achieved by using multi-level memory cells. With the new method, using staircase programming pulses combined with a bit-by-bit verify, a very narrow threshold voltage distribution of 0.7 V, necessary for 4-level or 2-bit operation, and a high programming speed of 300 /spl mu/s/page or 590 ns/byte can be obtained.

A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM

A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 μm. Using 1.0 μm rules, the cell size per bit is 11.7 μm2

A compact on-chip ECC for low cost flash memories

A compact on-chip Error Correcting Code/Circuit (ECC) for low cost Flash memories has been developed to minimize the chip size increase. The proposed on-chip ECC implemented on a 64 M NAND Flash memory has suppressed the chip size penalty to 1.9%. Moreover, the cumulative sector error rate can be improved by 4 orders after 10/sup 6/ write/erase cycles.

A 0.67 /spl mu/m/sup 2/ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs

An ultra high-density NAND-structured memory cell, using a new Self-Aligned Shallow Trench Isolation (SA-STI) technology, has been developed for a high performance and low bit cost 256 Mbit flash EEPROM. The SA-STI technology results in an extremely small cell size of 0.67 /spl mu/m/sup 2/ per bit, 67% of the smallest flash memory cell reported so far, by using a 0.35 /spl mu/m technology. The key technologies to realize a small cell size are (1) 0.4 um width Shallow Trench Isolation (STI) to isolate neighboring bits and (2) a floating gate that is self-aligned with the STI, eliminating the floating-gate wings. Even though the floating-gate wings are eliminated, a high coupling ratio of 0.65 can be obtained by using the side-walls of the floating gate to increase the coupling ratio. Using this self-aligned structure. A reliable tunnel oxide can be obtained because the floating gate does not overlap the trench corners, so enhanced tunneling at the trench corner is avoided. Therefore, the SA-STI cell combines a low bit cost with a high performance and a high reliability, such as the fast programming (0.2 /spl mu/sec/byte), fast erasing (2 msec), good write/erase endurance (>10/sup 6/ cycles), and excellent read disturb characteristics(>10 years). This paper describes the process technologies and the device performance of the SA-STI cell, which can be used to realize NAND EEPROMs of 256 Mbit and beyond.<<ETX>>

A reliable bi-polarity write/erase technology in flash EEPROMs

The authors describe a technology for scaling down the flash EEPROM cell, which has a conventional self-aligned double poly-Si stacked structure. It is clarified experimentally that a flash memory cell written and erased by Fowler-Nordheim (F-N) tunneling has ten times the retention time of the conventional cell, which is written by channel-hot-electron (CHE) injection and erased by F-N tunneling. This difference of data retentivity between these two write/erase (W/E) technologies is due to decreasing the thin gate oxide leakage current by bi-polarity F-N tunneling stress. This improvement in data retention becomes more pronounced as the gate oxide thickness decreases. Therefore, a bipolarity F-N tunneling WE technology, which enables a flash EEPROM cell to scale down its oxide thickness, shows promise as a key technology for realizing 16 Mb flash EEPROMs and beyond.<<ETX>>

Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (/spl Delta/V/sub th/) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high-temperature (125/spl deg/C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30/spl deg/C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures.

Advanced flash memory technology and trends for file storage application

This paper describes a high density flash memory technology suitable for file storage application. Requirements for file storage memory are low cost, high-speed programming and erasing, low power consumption and good endurance characteristics. In order to satisfy these requirements, key technologies of self-aligned STI (SA-STI) cell, uniform FN-FN program/erase scheme and multi-level-cell (MLC) technology have been developed. By using SA-STI technology, small cell size of 4F/sup 2/ (F: feature size) can be realized. Reliable tunnel oxide can be also obtained because the floating gate does not overlap the STI corner. As a result, reliable 512 Mbit flash memories with 0.145 um/sup 2/ cell size under 0.175 /spl mu/m design rule have been newly developed based on these technologies, as well as 0.25 /spl mu/m 256 Mbit. Moreover, MLC technology combined with this small cell size of 4F/sup 2/ can reduce bit cost more, and can expand the file storage market in the near future.

A novel high-density 5F/sup 2/ NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories

This paper describes a novel high density 5F/sup 2/ (F: feature size) NAND STI cell technology which has been developed for a low bit-cost flash memories. The extremely small cell size of 0.31 /spl mu/m/sup 2/ has been obtained for the 0.25 um design rule. To minimize the cell size, a floating gate is isolated with a shallow trench isolation (STI) and a slit formation by a novel SiN spacer process, which has made it possible to realize a 0.55 /spl mu/m-pitch isolation at a 0.25 /spl mu/m design rule. Another structural feature integral to the cell and its small size is the borderless bit-line and source-line contacts which are self-aligned with the select-gate. The proposed NAND cell with the gate length of 0.2 /spl mu/m and the isolation space of 0.25 /spl mu/m shows a normal operation as a transistor without any punch-through. Therefore, this 5F/sup 2/ NAND STI cell technology is essential to realize a low cost flash memories of 256 Mbit and 1 Gbit for mass-storage applications.

A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology

Higher density flash memories for mass storage are attractive for application in the audio-video field, for example, in digital cameras and for voice recording. A 100 MB Flash records one hour CD-quality music. Improvements in video compression techniques are expected to realize gigabyte flash, enabling movies on silicon in the near future; a development that is expected to lead to rapidly rising demand for high-density flash. Both the low bit cost due to the small cell size and the high program and read performance are important factors for the high density flash. A NAND flash has potential advantages in those respects. Shallow trench isolation (STI) shrinks bit line pitch to 73% of that in the case of conventional LOCOS isolation, enabling 0.29 um/sup 2/ cell 0.25 /spl mu/m design rules. The 129.76 mm/sup 2/ chip is made possible by using NAND type memory cell and STI.