James P. Di Sarro

Characterization of high-k/metal gate stack breakdown in the time scale of ESD events

Catastrophic gate oxide breakdown of MOSFETs with high-k gate was characterized under ESD-like pulsed stress. It was found that the excessive gate current after gate oxide failure may result in a loss of gate contact and form a resistive path between the drain and source. Using constant voltage stress (CVS) method, the gate oxide breakdown voltages (VBD) of NMSOFETs and PMOSFETs were extracted. NMOSFETs under positive stress were found to have the smallest VBD, while the VBD of the PMOSFETs under positive stress were significantly increased due to the well resistance. Compared to that measured using the CVS method, the VBD from the transmission line pulse method (TLP) was smaller by only less than 10%. Despite the cumulative damages caused by the TLP method, the result is a conservative estimation of the breakdown voltage. The VBD corresponding to the failure time of 1-ns measured using TLP method agrees well with the extrapolation result from the CVS measurements on the time scale ranging from ∼100 ns to ∼20 µs, suggesting that the failure mechanism remains the same as in the longer time scale.

Influence of Package Trace Properties on CDM Stress

CDM current waveform properties show a strong dependence on pin type and location due to package transmission line effects in large BGAs. I/O pin waveforms have a depressed peak, slower rise time, and increased pulsewidth compared to power supply waveforms, with the offset increasing with the distance from the package center. Simulations illustrate that the internal current through the ESD protection network on the die can deviate significantly from the external current observed in the CDM system for long package traces.