Hans Eisenmann

PROXECCO—Proximity effect correction by convolution

In electron‐beam lithography the proximity effect limits achieved resolution. A possible approach for proximity effect correction is the transform based method which uses deconvolution. This method requires high computing power and data reduction algorithms because of the small grid size. The fine grid is mainly needed for preserving pattern, not for the resolution of the correction. The new method called PROXECCO avoids this disadvantage by separating the calculation into correction related and pattern related steps. The grid size is spatially independent from pattern and can be as coarse as needed for correction. This results in a quadratical gain in computing time for the transformation. The pattern dimensions are kept exactly maintained and data reduction is not needed anymore.

Evaluation of a fast and flexible OPC package: OPTISSIMO

It is out of question, that current state-of-the-art lithography--printing 350 nm structures with i-line tools or 250 nm structures with DUV tools--needs to correct for proximity effects (OPC). Otherwise, all the well-known effects like line-end shortening, linewidth variation as a function of adjacent patterns, linewidth non-linearity, etc. will produce a pattern, that is significantly different from the intended design. In this paper, we report first evaluation results of OPTISSIMO, a software package for automatic proximity correction. Besides the ability to handle full-chip designs by preserving as much as possible of the original data-hierarchy, there are significant options for the user. A large number of choices can be made to balance between the precision of the correction and the complexity of the corrected design. The main target of our evaluations was to check for full-chip OPC for the gate level of a state-of-the-art design. This corresponds to print either linewidths in the 350 nm to 400 nm range with i-line lithography or 250 nm/300 nm linewidth with DUV lithography. Taking 400 nm i-line lithography as an example, 3% precision OPC which has been demonstrated. By using hierarchical data handling, it was shown, that even the data complexity of a 256 M DRAM can be managed within reasonable time.

Generalization of the photo process window and its application to OPC test pattern design

From the early development phase up to the production phase, test pattern play a key role for microlithography. The requirement for test pattern is to represent the design well and to cover the space of all process conditions, e.g. to investigate the full process window and all other process parameters. This paper shows that the current state-of-the-art test pattern do not address these requirements sufficiently and makes suggestions for a better selection of test pattern. We present a new methodology to analyze an existing layout (e.g. logic library, test pattern or full chip) for critical layout situations which does not need precise process data. We call this method “process space decomposition”, because it is aimed at decomposing the process impact to a layout feature into a sum of single independent contributions, the “dimensions” of the process space. This is a generalization of the classical process window, which examines defocus and exposure dependency of given test pattern, e.g. CD value of dense and isolated lines. In our process space we additionally define the dimensions resist effects, etch effects, mask error and misalignment, which describe the deviation of the printed silicon pattern from its target. We further extend it by the pattern space using a product based layout (library, full chip or synthetic test pattern). The criticality of pattern is defined by their deviation due to aerial image, their sensitivity to the respective dimension or several combinations of these. By exploring the process space for a given design, the method allows to find the most critical patterns independent of specific process parameters. The paper provides examples for different applications of the method: (1) selection of design oriented test pattern for lithography development (2) test pattern reduction in process characterization (3) verification/optimization of printability and performance of post processing procedures (like OPC) (4) creation of a sensitive process monitor.

Compensation of long-range process effects on photomasks by design data correction

CD requirements for advanced photomasks are getting very demanding for the 100 nm-node and below; the ITRS roadmap requires CD uniformities below 10 nm for the most critical layers. To reach this goal, statistical as well as systematic CD contributions must be minimized. Here, we focus on the reduction of systematic CD variations across the masks that may be caused by process effects, e.g. dry etch loading. We address this topic by compensating such effects via design data correction analogous to proximity correction. Dry etch loading is modeled by gaussian convolution of pattern densities. Data correction is done geometrically by edge shifting. As the effect amplitude has an order of magnitude of 10 nm this can only be done on e-beam writers with small address grids to avoid big CD steps in the design data. We present modeling and correction results for special mask patterns with very strong pattern density variations showing that the compensation method is able to reduce CD uniformity by 50 — 70 % depending on pattern details. The data correction itself is done with a new module developed especially to compensate long-range effects and fits nicely into the common data flow environment. For advanced photomasks the mask data preparation times have become a major issue. To tackle this fracture time increase distributed processing has been introduced into the photomask design flow. We also report first results on the fracture time reduction achievable by distributing the data correction onto a Linux cluster.

Proximity correction for high CD accuracy and process tolerance

Among the most important parameters in direct e-beam writing of ASICs is the control of linewidth. There are mainly two factors which endanger CD control: the proximity effect and topography on the wafer. For best possible CD beneath proximity correction the influence of topography on the linewidth must be respected. This paper presents an extension to the proximity correction package PROXECCO, which is designed to make CD deviations as insensitive as possible to dose errors over an estimated +/-20% range. The applied method, printed results and measurements are presented.

Proximity correction of high-dosed frame with PROXECCO

Usefulness of electron beam lithography is strongly related to the efficiency and quality of methods used for proximity correction. This paper addresses the above issue by proposing an extension to the new proximity correction program PROXECCO. The combination of a framing step with PROXECCO produces a pattern with a very high edge accuracy and still allows usage of the fast correction procedure. Making a frame with a higher dose imitates a fine resolution correction where the coarse part is disregarded. So after handling the high resolution effect by means of framing, an additional coarse correction is still needed. Higher doses have a higher contribution to the proximity effect. This additional proximity effect is taken into account with the help of the multi-dose input of PROXECCO. The dose of the frame is variable, depending on the deposited energy coming from backscattering of the proximity. Simulation proves the very high edge accuracy of the applied method.

Direct probing characterization vehicle test chip for wafer level exploration of transistor pattern on product chips

Due to recent changes in the manufacturing of FEOL (front end of line) layers it is increasingly difficult to provide rapid learning cycles required to drive yield improvement during new product introduction (NPI). The Direct Probe Characterization Vehicle (DPCV) Test Chip presented here provides direct access to thousands of transistors on a product chip. Only two masks are needed (contact & metal 1) to provide access to the DUTs of the unchanged FEOL layers of a product chip. The DPCV test chip is capable of matching the distribution of product transistor pattern. Measurement data indicate that corrective actions to the design and/or process recipes will reduce the gap between measured product chip transistors and their expected behavior based on SPICE simulations.

Force-Directed Placement of VLSI Circuits

The placement significantly influences the quality of a circuit. In the past decades a lot of placement algorithms were presented. The most popular ones are summarized here. Force-directed placers are able to place VLSI circuits with low wirelength within a suitable time. Examples for force-directed placers are Kraftwerk and Kraftwerk2, which start with an initial placement and use forces to evenly distribute the modules inside the placement area.

Geometrical correction of the e-beam proximity effect for raster scan systems

Increasing demands on pattern fidelity and CD accuracy in e- beam lithography require a correction of the e-beam proximity effect. The new needs are mainly coming from OPC at mask level and x-ray lithography. The e-beam proximity limits the achievable resolution and affects neighboring structures causing under- or over-exposion depending on the local pattern densities and process settings. Methods to compensate for this unequilibrated does distribution usually use a dose modulation or multiple passes. In general raster scan systems are not able to apply variable doses in order to compensate for the proximity effect. For system of this kind a geometrical modulation of the original pattern offers a solution for compensation of line edge deviations due to the proximity effect. In this paper a new method for the fast correction of the e-beam proximity effect via geometrical pattern optimization is described. The method consists of two steps. In a first step the pattern dependent dose distribution caused by back scattering is calculated by convolution of the pattern with the long range part of the proximity function. The restriction to the long range part result in a quadratic sped gain in computing time for the transformation. The influence of the short range part coming from forward scattering is not pattern dependent and can therefore be determined separately in a second step. The second calculation yields the dose curve at the border of a written structure. The finite gradient of this curve leads to an edge displacement depending on the amount of underground dosage at the observed position which was previously determined in the pattern dependent step. This unintended edge displacement is corrected by splitting the line into segments and shifting them by multiples of the writers address grid to the opposite direction.

Geometrical E-beam proximity correction for raster scan systems

High pattern fidelity is a basic requirement for the generation of masks containing sub micro structures and for direct writing. Increasing needs mainly emerging from OPC at mask level and x-ray lithography require a correction of the e-beam proximity effect. The most part of e-beam writers are raster scan system. This paper describes a new method for geometrical pattern correction in order to provide a correction solution for e-beam system that are not able to apply variable doses.