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Sherry Lee

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Featured researches published by Sherry Lee.

international conference on solid state and integrated circuits technology | 2001

Test structures based VLSIC yield ramp maximization

Andrzej J. Strojwas; Dennis Ciplickas; Sherry Lee

This paper addresses a new approach to yield learning of lead products in the most advanced technologies. We start by presenting the classification and evolution of yield loss mechanisms in the most recent and upcoming technology generations. Then we show a spectrum of yield loss characterization methods, from in-line to E-test to product test analysis. The main part of the paper is devoted to the presentation of specially designed test structures for the diagnosis of the dominant yield loss components such as random defects, and systematic and parametric effects.

Archive | 2003

Designing an integrated circuit to improve yield using a variant design element

Dennis Ciplickas; Joseph C. Davis; Christopher Hess; Sherry Lee; Enrico Malavasi; Abdulmobeen Mohammad; Ratibor Radojcic; Brian E. Stine; Rakesh Vallishayee; Stefano Zanella; Nicola Dragone; Carlo Guardiani; Michel Quarantelli; Stefano Tonello; Joshi Aniruddha

Archive | 2003

Fast localization of electrical failures on an integrated circuit system and method

Dennis Ciplickas; Christopher Hess; Sherry Lee; Larg Weiland

Archive | 2016

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2018

Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2018

Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2018

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2017

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2017

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on wafers that include multiple steps for enabling NC detecteion of AACNT-TS via opens

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2017

Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

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Dennis Ciplickas

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Christopher Hess

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Andrzej J. Strojwas

Carnegie Mellon University

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John Kibarian

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Kimon Michaels

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Rakesh Vallishayee

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Carl Taylor

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Conor O'sullivan

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Hans Eisenmann

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Hideki Matsuhashi

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