Randy L. Wolf

A Thin-Film SOI 180nm CMOS RF Switch Technology

This paper describes a 180nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS

A low-cost test solution for wireless phone RFICs

This article describes an IBM approach for testing high-volume, complex RFICs at a fraction of the cost of the integrated circuit. This approach uses a personal computer, a fast benchtop dc parametric analyzer, and RF-to-analog circuits to test an RFIC during the manufacturing process. The described system and methodology are specifically designed for high-volume test, where test cost is extremely important; they are not recommended for lower-volume products (less than 1 million per month). This article describes the system architecture and discusses design, maintenance, and implementation considerations. The system is designed to reduce the cost of a complex RFIC manufacturing test to equal that of a discrete component, such as a resistor or capacitor. Given the relatively easy implementation and the drastic cost reduction associated with the test solution, this architecture establishes a new standard for the future of RF test. In fact, this architecture may result in the fastest RF tester currently available.

Architecting millisecond test solutions for wireless phone RIFIC's

Todays low cost wireless phones have driven a need to be able to economically test high volumes of complex RF ICs at a fraction of the cost of the IC. In June of 2001 the IBM test development group developed a strategy and design to test complex wireless phone front end components for a fraction of the cost of using traditional ATE or rack and stack test solutions. In this paper, the architecture of the system is described as well as some of the design, maintenance and implementation considerations. The system is designed to bring the cost of complex manufacturing test of RF ICs equivalent to that of testing discrete components such as resistors or capacitors. Given the drastic reduction of test cost and the relative ease of implementation of this solution, this architecture sets the bar for future RF test solutions. To the best of our knowledge, this architecture has resulted in the fastest RF tester in the world.

RF testing on a mixed signal tester

In this paper, testing of radio frequency (RF) devices with mixed-signal testers is discussed. General purpose automatic test equipment (ATE) will be used. In this paper, a more universal test structure utilizing RF building blocks is proposed. A global positioning system (GPS) device is used as an example to illustrate how to develop the RF test plan with this usage. The test plan developed includes fast, cost-effective and dedicated circuitry.

High performance SOI RF switches for wireless applications

This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for SOI RF switch designs for wireless applications. The measured results of SP4T (single pole four throw) and SP8T (single pole eight throw) switch reference designs are presented. It has been demonstrated that SOI RF switch performance, in terms of power handling, linearity, insertion loss and isolation, is very competitive with those utilizing GaAs pHEMT and silicon-on-sapphire (SOS) technologies, while maintaining a cost and manufacturing advantage.

A Thin-Film SOI 180nm CMOS RF Switch

This paper describes a single pole, single throw (SPST) 180nm CMOS thin film SOI switch developed for the most difficult cellular and 802.11x RF switch applications. We will show that power handling, linearity, insertion loss, isolation and switching times are competitive with switch applications utilizing GaAs pHEMT and silicon- on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS I. INTRODUCTION The majority of transceivers in wireless communication systems require a switch to provide isolation between the transmitter and receiver, and flexibility in connecting the antenna(s) to the transmitter or receiver optimized for the needed communication standard in multi-mode systems. In addition to having sufficient isolation, a switch requires low insertion loss to maintain high transmitter efficiency and low receiver noise figure. High linearity is important to ensure that the amplitude and phase information of the modulated signal is maintained and to prevent intermodulation distortion. Switching times much faster than 1us are important in standards such as 802.11a (1) to ensure the full amount of power is available to or from the antenna when required. These performance requirements have historically motivated the selection of GaAs (2) or silicon-on-sapphire (SOS) technologies (3) for RF switch applications. These technologies provide a semi-insulating or insulating substrate, respectively, that offer small substrate parasitic coupling. Reduced substrate coupling minimizes insertion loss, removes a significant source of harmonic frequency generation, and helps ensure uniform voltage division in the stacked transistor configurations that are required for high power applications. However, integrating multi- mode and multi-band capabilities forces a complex integration of T/R switches, e.g. single-pole nine-throw (SP9T). Such complex switch integration requires high- yielding technology such as silicon based CMOS. GaAs and SOS technologies suffer cost and/or integration disadvantages in comparison with purely silicon technologies. Several authors have investigated RF switches fabricated on silicon wafers using nMOS as the switch device (4-6). Recent technology and design improvements have been closing the gap between silicon switch implementations and GaAs or SOS approaches. This paper describes several SPST switch configurations that have been built using the 180nm silicon-on-insulator (SOI) technology optimized for RF switch applications (7), and their measured results. How these measured results compared to simulations and other technologies are also discussed.

Silicon solutions for RF front-end applications

The 4th generation wireless standard is ushering an era of ubiquitous connectivity. The convergence of data and voice to a portable media device is producing an explosive demand for high data rate communication. Such convergence requirements along with the need for improved battery life, smaller form factor, and reduced cost will demand new ways of system integration. The RF front-end-modules (FEM) that incorporates Power Amplifiers (PAs), Switches, power controller, and passives is one of the segment that is seeing major advancements. Silicon solutions are starting to penetrate into this GaAs stronghold. We discuss the potential for silicon-based technology in providing capability for FEM integration.

Statistical variations in VCO phase noise due to upconverted MOSFET 1/f noise

Statistical phase noise analysis and measurements are presented for a population of RF CMOS VCOs. The measured mean values for phase noise at 1 kHz and 1 MHz offset frequencies are -46 dBc/Hz and -130 dBc/Hz respectively. However a large variation from the mean (+/-3 dBc/Hz) is observed for the close-in phase noise. This variation is attributed to the upconverted transistor 1/f noise and its statistical nature. Phase noise simulations employing two versions of models with 1/f noise statistics have been run and compared to measurement. The improved noise model which accounts for the bias dependence of noise variability shows excellent agreement with measured data, while the early model with no bias dependence overpredicts the phase noise variations.

Power handling capability of an SOI RF switch

In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.

Improvements in SOI technology for RF switches

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.