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Publication
Featured researches published by Robb Allen Johnson.
IEEE Transactions on Electron Devices | 2001
David L. Harame; David C. Ahlgren; Douglas D. Coolbaugh; James S. Dunn; G. Freeman; John D. Gillis; Robert A. Groves; Gregory N. Hendersen; Robb Allen Johnson; Alvin J. Joseph; Seshardi Subbanna; Alan M. Victor; Kimball M. Watson; Charles S. Webster; P.J. Zampardi
The silicon germanium (SiGe) heterojunction bipolar transistor (HBT) marketplace covers a wide range of products and product requirements, particularly when combined with CMOS in a BiCMOS technology. A new base integration approach is presented which decouples the structural and thermal features of the HBT from the CMOS. The trend is to use this approach for future SiGe technologies for easier migration to advanced CMOS technology generations. Lateral and vertical scaling are used to achieve smaller and faster SiGe HBT devices with greatly increased current densities. Improving both the f/sub T/ and f/sub MAX/ will be a significant challenge as the collector and base dopant concentrations are increased. The increasing current densities of the SiGe HBT will put more emphasis on interconnects as a key factor in limiting transistor layout. Capacitors and inductors are two very important passives that must improve with each generation. The trend toward increasing capacitance in polysilicon-insulator-silicon (MOSCAP), polysilicon-insulator-polysilicon (Poly-Poly), and metal-insulator-metal (MIM) capacitors is discussed. The trend in VLSI interconnections toward thinner interlevel dielectrics and metallization layers is counter to the requirements of high Q inductors, potentially requiring a custom last metallization layer.
bipolar/bicmos circuits and technology meeting | 2001
Alvin J. Joseph; D. Coolbaugh; Michael J. Zierak; R. Wuthrich; Peter J. Geiss; Zhong-Xiang He; Xuefeng Liu; Bradley A. Orner; Jeffrey B. Johnson; G. Freeman; David C. Ahlgren; Basanth Jagannathan; Louis D. Lanzerotti; John C. Malinowski; Huajie Chen; J. Chu; Peter B. Gray; Robb Allen Johnson; James S. Dunn; Seshadri Subbanna; Kathryn T. Schonenberg; David L. Harame; R. Groves; K. Watson; D. Jadus; M. Meghelli; A. Rylyakov
A BiCMOS technology is presented that integrates a high performance NPN (f/sub T/=120 GHz and f/sub max/=100 GHz), ASIC compatible 0.11 /spl mu/m L/sub eff/ CMOS, and a full suite of passive elements. Significant HBT performance enhancement compared to previously published results has been achieved through further collector and base profile optimization guided by process and device simulations. Base transit time reduction was achieved by simultaneously increasing the Ge ramp and by limiting the base diffusion with the addition of carbon doping to SiGe epitaxial base. This paper describes IBMs next generation SiGe BiCMOS production technology targeted at the communications market.
electrical overstress electrostatic discharge symposium | 2000
Steven H. Voldman; P. Juliano; J. Schmidt; Robb Allen Johnson; Louis D. Lanzerotti; Alvin J. Joseph; Ciaran J. Brennan; James S. Dunn; David L. Harame; Elyse Rosenbaum; Bernard S. Meyerson
This paper investigates high-current and electrostatic discharge (ESD) phenomena in pseudomorphic epitaxial-base silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in base-collector, base-emitter, collector-emitter and collector-to-substrate configurations. Transmission line pulse (TLP) and ESD human body model (HBM) wafer-level reliability testing of SiGe HBTs is completed for high-current characterization and evaluation of the ESD robustness of a BiCMOS SiGe technology.
bipolar/bicmos circuits and technology meeting | 1999
S. St Onge; David L. Harame; James S. Dunn; Seshadri Subbanna; David C. Ahlgren; G. Freeman; Basanth Jagannathan; J. Jeng; Kathryn T. Schonenberg; Kenneth J. Stein; R. Groves; D. Coolbaugh; Natalie B. Feilchenfeld; Peter J. Geiss; M. Gordon; Peter B. Gray; Douglas B. Hershberger; S. Kilpatrick; Robb Allen Johnson; Alvin J. Joseph; Louis D. Lanzerotti; John C. Malinowski; Bradley A. Orner; Michael J. Zierak
A new base-after-gate integration scheme has been developed to integrate a 47 GHz f/sub t/, 65 GHz F/sub max/SiGe HBT process with a 0.24 /spl mu/m CMOS technology having 0.18 /spl mu/m L/sub eff/ and 5 nm gate oxide. We discuss the benefits and challenges of this integration scheme which decouples the HBT from the CMOS thermal cycles. We also describe the resulting 0.24 /spl mu/m SiGe BiCMOS technology, BiCMOS 6HP, which includes a 7 nm dual gate oxide option and full suite of passive components. The technology provides a high level of integration for mixed-signal RF applications.
international reliability physics symposium | 2000
James S. Dunn; D. L. Harame; S. St Onge; Alvin J. Joseph; Natalie B. Feilchenfeld; K. Watson; Seshadri Subbanna; G. Freeman; Steven H. Voldman; David C. Ahlgren; Robb Allen Johnson
A base-after-gate integration scheme has been developed fora 0.25 /spl mu/m SiGe BiCMOS and the details of the approach are discussed. NPN device reliability is reviewed for high-frequency transistors. The reliability aspects associated with using SiGe for applications with high collector-base voltage with high emitter current are also explored. Finally, the ESD characteristics of the SiGe BiCMOS technology elements are summarized.
bipolar/bicmos circuits and technology meeting | 2000
Steven H. Voldman; Patrick Juliano; N. Schmidt; A. Botula; Robb Allen Johnson; Louis D. Lanzerotti; Natalie B. Feilchenfeld; J. Joseph; John C. Malinowski; E. Eld; V. Gross; C. Brennan; James S. Dunn; David L. Harame; D. Herman; Bernard S. Meyerson
High current characterization of epitaxial-base pseudomorphic silicon germanium heterojunction npn bipolar transistors (HBT) for evaluation of the electrostatic discharge (ESD) robustness is reported. BiCMOS active and passive elements are discussed.
international symposium on the physical and failure analysis of integrated circuits | 2001
Steven H. Voldman; Louis D. Lanzerotti; Robb Allen Johnson
With the growth of the high-speed data rate transmission, optical interconnect, and wireless marketplaces, heterojunction devices will play a central role in these communication systems. Heterojunction base-emitter design, bandgap engineering and technology scaling will each play a key role in the ability to achieve faster devices for the wired and wireless markets. As these structures are scaled, the sensitivity of these devices to electrostatic overstress (EOS), electrostatic discharge (ESD) and electromagnetic emissions (EMI) becomes a concern. Emitter-base design influences the ESD sensitivity and device performance of heterojunction bipolar transistor (HBT) devices. In this paper, the ESD sensitivity of the emitter-base junction of a SiGe HBT device is discussed. The evaluation of process variations and device design spacings on ESD robustness is evaluated for both positive and negative stress conditions as a function of the salicide location, emitter-base spacing, and collector opening.
Archive | 2004
Marc W. Cantell; James S. Dunn; David L. Harame; Robb Allen Johnson; Louis D. Lanzerotti; Stephen A. St. Onge; Brian L. Tessier; Ryan W. Wuthrich
Archive | 2000
Steven H. Voldman; Robb Allen Johnson; Louis D. Lanzerotti; Stephen A. St. Onge
Archive | 2004
Jack O. Chu; Douglass Duane Coolbaugh; James S. Dunn; David R. Greenberg; David L. Harame; Basanth Jagannathan; Robb Allen Johnson; Louis D. Lanzerotti; Kathryn T. Schonenberg; Ryan W. Wuthrich