Ryo Tanabe

Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs

In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We proposed a flip-flop of SET-SEU-RHBD. This flip-flop has LPF using a C-element with dual transmission and applies an MNL technique only on the master latch. This flip-flop is designed with 45-nm technology and a 16-grid height. Mitigation efficiencies of the flip-flop are estimated by accelerated experiments and simulations. The flip-flop can protect 90% of SEU and 52 ps SET pulse with low penalties.

Investigation of SNM with Random Dopant Fluctuations for FD SGSOI and FinFET 6T SOI SRAM Cell by Three-dimensional Device Simulation

As CMOS technology is dramatically scaled down in recent years, the operation of SRAM becomes one of critical issues for further scaling. In this paper, we have focused on both FD SGSOI and DG (FinFET) devices because of the scaling capabilities, and we have simulated SRAM SNM with discrete dopant fluctuations in the channel regions by 3D simulation. As for SNM, FinFET is a promising candidate up to 32 nm node, but for 22 nm node, it will be difficult to operate even a FinFET with stability. As for fluctuations, the total number of dopant in channel depletion layer is a key factor. The fluctuations of SNM in FinFET are reduced by balancing fin thickness and dopant density in the channel

Mitigation technique against multi-bit-upset without area, performance and power overhead

In this work, we propose a technique for mitigating multi-bit-upset (MBU) which cannot be corrected by Error-Correction-Code (ECC) with using bit-line alternation and narrow deep-N-well. This technique mitigates MBU without area, performance and power overhead. The mitigation efficiency is evaluated with alpha and neutron acceleration experiments. The experimental results show excellent mitigation efficiency of the proposed technique.

Compact Double-Gate MOSFET Model Correctly Predicting Volume-Inversion Effects

The compact double-gate MOSFET model HiSIM-DG considering the volume inversion effects is developed solving the Poisson equation iteratively including bulk charge. The developed model reproduces the bias dependence of not only the surface but also the center potential of the silicon layer. The model proves accurate dependence of silicon layer thickness in comparison to the 2 dimensional device simulation results. It is observed that the volume inversion effect prevents devices from performance degradation for a reduction of device sizes.

Exploring Well-Configurations for Minimizing Single Event Latchup

This work experimentally studies single event latchup (SEL) prevention by altering well configurations. The well structures under consideration in this paper are ordinary twin-well structure, triple-well structure with deep N-well (DNW) and triple-well structure with deep P-well (DPW). Doping profiles are also varied in our experiments. Neutron irradiation tests for test chips fabricated in 55-nm and 90-nm bulk Si CMOS processes show that SEL can be suppressed with a DPW or a DNW well configuration and a high-dose implantation in the well. Among these, DPW was the most effective to eliminate SEL, and no SEL was observed throughout our irradiation tests in the SRAM with DPW in both 55-nm and 90-nm processes. In addition, DPW brings a desirable side effect of single event upset (SEU) reduction. A disadvantage is a cost to develop a DPW process. DNW is a common process option and hence it is easily adopted for SEL prevention, but we need to pay attention to the fact that DNW increases SEU rate. Increasing well doping in twin-well structure reduced SEL by 60%.

Soft Error Hardened Latch and Its Estimation Method

We propose soft error robust latches which have multi storage nodes and present their efficiencies. The key technology of the latch is a feedback loop circuit with a data node and four gates. We also discuss a method of soft error estimation in robust circuits in this paper. The soft error immunity of this feedback loop circuit is estimated by circuit simulations with two models. The soft error immunity of the latch is estimated by device simulation more accurately. By these precise simulations, the latch is proven to be highly tolerant to soft errors. In addition, the latch protects from not only retention data upset but also transient noise releasing. The latch provides high immunity against all soft error problems with a simple circuit. It is easy to apply the latch technique to various latches, such as single latches, scan latches, and flip-flops.

Analytical Threshold Voltage Model for Double-Gate Schottky Source/Drain Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

We modify a theoretically derived model for double-gate silicon-on-insulator metal oxide semiconductor field effect transistor (SOI MOSFET) and establish new analytical threshold voltage model for double-gate Schottky source/drain SOI MOSFET. We show the procedure for deriving this model and present a high accuracy of this model in comparison with the numerical data obtained with a two-dimensional device simulator. We found that we can get the same natural length obtained using a conventional double-gate device and better short-channel effect suppression using double-gate Schottky source/drain SOI MOSFET. Our analytical model can be used for designing Schottky barrier MOSFET with efficiency and accuracy.

Suppressed Short-Channel Effect of Double-Gate Metal Oxide Semiconductor Field-Effect Transistor and Its Modeling

The double-gate (DG) metal oxide semiconductor field-effect transistor (MOSFET) is considered to be a promising for the next-generation device. We have developed a model describing the short-channel effects of the DG-MOSFET. The model describes suppression of the short-channel effect with the reduction of the silicon layer thickness. Modeling for further suppression of the short-channel effect is achieved by considering the volume inversion effect. The developed model reproduces the suppressed short-channel effect of the DG-MOSFET as a function of the silicon layer thickness down to 10 nm for any gate length with three model parameters.

Preventing single event latchup with deep P-well on P-substrate

We propose a method that prevents single event latchup (SEL) using deep P-well on P-substrate. To confirm the effectiveness of the proposed method, SEL and single event upset (SEU) are evaluated for three well configurations; double-well, ordinary triple-well and the proposed deep P-well on P-substrate. Neutron irradiation test shows that the proposed method achieves SEL prevention without SEU increase.

Analytical Model for Two-Dimensional Ion Implantation Profile in MOS-Structure Substrate

We derived an analytical model to obtain a 2-D impurity concentration profile for ions implanted at high-tilt angles in MOS-structure substrates. This model enabled us to simulate MOS device characteristics with a fully analytical impurity distribution where diffusion was neglected. We tested and verified that our analytical model could provide the same results as the ones obtained using a 2-D process simulator.