Shigeo Satoh

A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

A novel CMOS architecture utilizing tensile/compressive silicon nitride capping layers to induce tensile/compressive strain in NMOSFET/PMOSFET channel regions was developed. NMOSFET device delivers 1.05mA//spl mu/m on-current for 70nA//spl mu/m off-current at IV drain voltage. PMOS device exhibits peak 66% increase of linear drain current and 55% increase of saturation current. It was shown that drain current improvements both for N- and PMOSFETs strongly correlate with channel doping levels. Therefore, advanced methods of shallow and low resistance junction formation are required for maintaining low channel doping concentration and efficiently utilizing channel strain at sub-40nm gate length.

Simulation technologies for cosmic ray neutron-induced soft errors: Models and simulation systems

The authors review two types of simulators for the analysis of cosmic ray neutron-induced soft errors (SEs). One of them is the neutron-induced soft error simulator (NISES). A recently proposed nuclear reaction theory forms the foundation for the nuclear reaction database used in NISES. The other simulator, the simplified simulator MBGR, is based on a modified version of the burst generation rate (BGR) model. Both simulators accurately simulate neutron-induced SE rates (SERs). MBGR actually provides an easier and quicker estimation of neutron-induced SERs than NISES. On the other hand, NISES covers more applications: it simulates neutron-induced charge collection, multiple-bit SE, and /spl alpha/-induced SE analysis.

Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits

Neutron-induced soft error rates (SERs) of subhalf-micron CMOS SRAM and Latch circuits were studied both experimentally and analytically to investigate cosmic ray neutron-induced soft errors (SEs). Because the neutron beam used in the measurement has an energy spectrum similar to that of sea-level atmospheric neutrons, our SER data corresponds to those induced by cosmic ray neutrons. The /spl alpha/-particle induced SERs were also measured for comparison with the neutron-induced SERs. Neutron-induced SEs occurred in both circuits. On the other hand, /spl alpha/-induced SEs occurred in SRAM, but not in the Latch circuits. The measured SERs agreed with simulated results. We discussed the significance of how cosmic ray neutrons affects CMOS circuits at ground level.

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A//spl mu/m and 690/spl mu/A//spl mu/m at V/sub dd/=1V/I/sub off/=100nA//spl mu/m, respectively. This is the best drive current among the recent reports.

Neutron-induced soft-error simulation technology for logic circuits

In this paper, we describe the simulation technology used to estimate soft errors in logic circuits. The neutron induced soft-error simulator (NISES), which was previously developed for estimating soft-errors in memories is applied to the estimating soft errors in latch circuits and its effectiveness is shown. We model soft-error phenomena in combinational circuits and develop a novel simulation system for estimating soft errors in such circuits. Estimated results show that soft-error rate increases in combinational circuits as technology advances. Soft errors in logic circuits will thus become crucial.

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 /spl mu/m/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

This paper presents a 65 nm CMOS technology for mobile multimedia applications. The reduction of interconnect capacitance is essential for high-speed data transmission and small power consumption for mobile core chips. We have chosen a hybrid ULK structure which consists of NCS (nano-clustering silica; k=2.25) at the wire level and SiOC (k=2.9) at the via level. Although NCS is a porous material, the NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bonding. Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistors meet the electrical targets from the circuit requirements. Moreover, an embedded 6T-SRAM with a 0.55 /spl mu/m/sup 2/ small cell size has been achieved.

Measurements and analysis of neutron-reaction-induced charges in a silicon surface region

We directly measured neutron-reaction-induced charges in the silicon surface region using silicon-on-insulator (SOI) test structures. Because the neutron beam used has an energy spectrum similar to that of sea-level atmospheric neutrons, our charge collection data correspond to those induced by cosmic ray neutrons. Measured charge collection spectra were dependent on the SOI thickness and agreed with simulated results. An application for the neutron-induced upset rate prediction was also discussed. Furthermore, the charge collection components were separated by our charge collection simulator.

CMOS-SRAM soft-error simulation system

We present a soft-error simulation system for designing CMOS-SRAM cells. We proposed a new noise current model and combined it with the SRAMs equivalent circuit. Using a three-dimensional topography simulator and considering the Rutherford scattering, we obtained the exact injection probability. The simulation results agree with those from a compulsory exposure experiment. Our system predicts the field soft-error rate from the alpha-particle emission rate, mask layout, and process conditions.<<ETX>>

Analytical Models for Symmetric Thin-Film Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistors

We derived analytical models for the current-voltage characteristics of double-gate silicon-on-insulator metal-oxide-semiconductor-field-effect-transistors. In the subthreshold region, we derived an analytical subthreshold slope model considering both depleted and induced charges. We proposed a unique definition of threshold voltage of the device, and showed that the threshold voltage is close to the experimentally defined threshold voltage at which the drain current has a specific value. The variation in the surface potential after the threshold voltage was modeled, and hence the models are valid in the moderate-inversion region as well as in the strong-inversion region. The models agree well with experimental data.

Novel Extraction Method for Size-Dependent Mobility Based on BSIM3-Like Compact Model

We applied a BSIM3-like compact model in order to analyze size dependent low field mobility in MOSFETs. By using the newly proposed extraction method, we have successfully extracted the gate length dependence of mobility degradation due to halo doping and the mobility enhancement due to mechanical stress. Moreover, parasitic resistance at source and drain Rsd has been accurately extracted in a variable mobility case. The new method is applicable to wide ranges of device sizes, structures and materials.