Ryu Ogiwara

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor

A 0.5-/spl mu/m, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a temperature dependence. A variable reference voltage scheme is generated to solve this problem, boosting a fatigue-free and temperature-independent MOS reference capacitance by a driver. The driver is operated from a compact reference voltage generator that provides 32 equally divided voltages and occupies only half the layout area of a conventional one. During sense operation, memory-cell capacitance C/sub ferr/ is larger than reference-cell capacitance C/sub MOS/. A double word-line pulse scheme has also been developed to eliminate a bit-line capacitance imbalance in the bit-line pairs, where a memory cell and a reference cell are separated from the bit-line pairs during sense operation. A six-order improvement in imprint lifetime has been achieved by the new scheme.

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 mu m/sup 2/, using 0.4- mu m CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm/sup 2/, which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved. >

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst

A 32-Mb chain FeRAM with segment/stitch array architecture

A 96mm/sup 2/, 32Mb chain FeRAM in 0.20/spl mu/m 3M CMOS and stacked capacitor technology is described. Cell efficiency of 65.6% is realized by compact memory cell structure and segment/stitch WL architecture. The word line power-on/off sequence protects the data from startup noise. A 3/spl mu/A standby current bias generator and compatible access mode SRAM are implemented for mobile applications.

A 76 mm/sup 2/ 8 Mb chain ferroelectric memory

An 8 Mb chain FeRAM uses 0.25 /spl mu/m 2-metal CMOS technology. A one-pitch-shift cell realizes 5.2 /spl mu/m/sup 2/ cell area. A chain architecture with a hierarchical wordline scheme gives 76 mm/sup 2/ die. Random access time is 40 ns, and cycle time is 70 ns at 3.0 V.

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-“0”-write-before-data-write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm2.

FRAM cell design with high immunity to fatigue and imprint for 0.5 /spl mu/m 3 V 1T1C 1 Mbit FRAM

A new FRAM cell design with high immunity to fatigue and imprint has been proposed to achieve a megabit class FRAM with 1T1C cell structure, which has been applied to a 1M bit FRAM operated from a 3 V supply with 1T1C cell structure, 0.5 /spl mu/m rule and 3 /spl mu/m/sup 2/ capacitor area. The simulation result and imprint data predict a lifetime improved 7 orders longer than the conventional scheme.

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both “1” and “0” data. The reference bitline bias of 64 Mb chip is designed to keep intermediate value of “1” and “0” data at any operating temperatures from -40^°C to 85 ^°C by introducing a modified band-gap reference circuit with 3 bit temperature coefficient trimmers and 6 bit digital-to-analog converter (DAC) using laser fuses. The measured result shows the improvement of tail-to-tail cell signal windows by ±22 mV. Moreover, a new reference bias circuit called the “elevator circuit” with 3 bit temperature coefficient trimmers using ferroelectric fuses installed in a 128 Mb chip compensates array operating voltage VAA fluctuation as well as temperature variation. The elevator circuit enables the temperature dependency control at low external VDD of 1.8 V. This improves cell signal window by ±40 mV. The elevator circuit also varies reference bitline bias with array operating voltage VAA variation, resulting in improvement of cell signal windows by ±44 mV in the range of 1.5 V ±0.2 V VAA.

Word-line architecture for highly reliable 64-Mb DRAM

A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10/sup 5/ times reliability improvement and a 0.3 approximately 1.8-V larger word-line voltage margin to write ONE data into the cell. >