S. Bronckers

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 mm2 and 65 mW. The presented receiver targets 60 GHz communication where beamforming is required.

A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS

In this paper, a CMOS implementation of phased-array receiver front-end, based on a widely tunable QVCO is presented. Each path achieves 30dB of gain and a minimum NF of 7.1dB, yielding a system NF of 4.1dB. The overall current draw is 54mA from a 1.2V supply. Additionally, a calibration procedure to mitigate the analog impairments imposed by the proposed implementation is demonstrated.

Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5–7 GHz

The coupling of the transmitted radio-frequency (RF) signal of the power amplifier (PA) in the sensitive voltage-controlled oscillator (VCO) remains a major problem for system-on-chip (SoC) design. Coupling between these two circuits may cause malfunctioning of the system. This paper analyzes the different coupling mechanisms between a 4 GHz prepower amplifier (PPA) and a 5-7 GHz LC-VCO designed in 0.13 mum technology. Different experiments are carried out to reveal the dominant coupling mechanisms. Insight into these mechanisms leads to the proposal of proper countermeasures.

LC

Software-defined multi-standard radios are emerging solutions for future mobile applications. Expensive scaled CMOS processes are readily used as a technology enabler to provide adequate performance. The high implementation cost of circuits in such processes is justified by the added functionality of the circuits, however it also drives the desire for low-area solutions in standard digital CMOS. For example, low-area inductor-less LNAs take advantage of the high ft of scaled CMOS. Unfortunately, stringent phase noise requirements make inductors unavoidable in VCOs. This leads to solutions with area-demanding multiple- inductor synthesizers or spur-hazardous multiply-and-divide sections to cover the wide frequency range required for multi- standard receivers. In this work, we demonstrate a low-area multi-standard direct downconversion receiver front-end that uses a single-inductor dual-band VCO and is implemented in 90 nm digital CMOS.

-VCO

Substrate noise issues are a showstopper for the smooth integration of analog and digital circuitries on the same die. For the designer, it is not known how substrate noise couples into the transistors of the analog circuitry. This paper reveals the dominant coupling mechanisms with simulations and the corresponding measurements in a 0.13-¿m triple-well common-source complementary metal-oxide-semiconductor (CMOS) transistor integrated on a lightly doped substrate. Substrate noise couples in either the ground or the bulk of the transistor. It is demonstrated that the importance of the coupling mechanisms depends on the resistance of the ground interconnect. For the technology node used, measurements show that substrate noise isolation is optimal for a ground resistance of 0.8 ¿.

A Single-Inductor Dual-Band VCO in a 0.06mm 2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS

Substrate noise problems in a system-on-a-chip hamper the smooth cohabitation between analog and digital circuitries on the same die. Solving those problems will shorten the time to market. This paper presents a methodology that gives designers the necessary insight to solve this substrate noise problem. The methodology combines the strengths of the electromagnetic simulator, the parasitic extractor, and the circuit simulator. Its main assets are the ease of use, an acceptable simulation time, and a good accuracy. Moreover, this methodology does not need doping profiles that are hard to get hold off. The proposed methodology is demonstrated on two challenging examples: a 48-53-GHz LC voltage-controlled oscillator and a dc-to-5-GHz wideband receiver designed, respectively, in a 0.13-mum and a 90-nm CMOS technology. The substrate noise coupling mechanisms are revealed for both examples in a simulation time of less than 2 hours. The methodology is successfully validated by measurements performed on real-life prototypes of those examples with an accuracy of 1-2 dB.

Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors

The coupling of the transmitted RF signal of the power amplifier (PA) into the sensitive voltage controlled oscillator (VCO) of a transceiver can cause failure of the RFIC. It is not obvious for the designer to identify which coupling mechanism can be held responsible for the degradation of the VCO. Thus it remains an open problem to decide which appropriate countermeasure should be taken. Different experiments are carried out on a 0.13 mum CMOS 4 GHz PPA and a 5-7 GHz LC-VCO to gain insight in the different coupling mechanisms.

A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems

Substrate noise coupling remains a major problem for a system on a chip (SoC) design. Coupling between various parts of the system through the substrate may cause malfunctioning of the system. Guard rings are frequently used to shield the analog circuitry from the noisy digital circuits. In this paper measurements show that the isolation does not increase linearly with the guard ring width. These experimental results reveal that starting from a guard ring width above 16 mum, the isolation saturates with the guard ring width. It also shows that the effectiveness of the guard ring strongly depends on its ground connection. The effectiveness of the proposed guard rings against substrate noise is demonstrated on a 5-7 GHz LC voltage controlled oscillator (VCO), designed in a CMOS 130 nm technology.

Study of the different coupling mechanisms between a 4 GHz PPA and a 5–7 GHz LC-VCO

This paper presents a methodology for the analysis and prediction of the impact of wideband substrate noise on a LC-Voltage Controlled Oscillator (LC-VCO) from DC up to Local Frequency (LO). The impact of substrate noise is modeled a priori in a high-ohmic 0.18μm 1P6M CMOS technology and then verified on silicon on a 900MHz LC-VCO. Below a frequency of 10MHz, the impact is dominated by the on-chip resistance of the VCO ground, while above 10MHz the bond wires, parasitics of the on-chip inductor and the PCB decoupling capacitors determine the behavior of the perturbation.

On the P+ guard ring sizing strategy to shield against substrate noise

Substrate noise problems continue to harass the design of a System-on-a-Chip (SoC). It is not obvious for the designer to identify the dominant substrate noise entry points. This paper proposes a new approach to gain insight in and predict the impact of substrate noise on mm-wave circuits. The approach is validated by measurements on a CMOS 48-53 GHz LC-VCO, designed in a UMC 0.13 μm technology.