S. H. Bae

Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration

This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel Vt of ~plusmn0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack

Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/ gate dielectric. The wet etch of TaSiN had a minimal impact on HfO/sub 2/ (/spl Delta/EOT<1/spl Aring/). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L/sub g/ down to 85nm.

Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.

Impact of plasma induced damage on pMOSFETs with TiN/Hf-silicate stack

We report on the plasma induced damage in the TiN/HfSiO/sub 4/ gate stack, and, specifically, its impact on pMOSFETs. Plasma assisted deposition processes after the gate stack etch step appear to cause most plasma damage, manifested by greater degradation of the plate antenna structures (area intensive) compared to comb antennas (perimeter intensive). The transient charge trapping behavior of the HfSiO/sub 4/ film seems to prevent destructive dielectric breakdown. Electrical stress could generate additional traps in the film damaged by the plasma process.

Improved Gate-Edge Profile of Metal/High-k Gate Stack Using an NH3 Ashing Process in Gate-First CMOSFETs

This study analyzed an alternative ashing technology for removing photoresist in the production of gate-first complementary metal oxide semiconductor field effect transistors (CMOSFETs) with a high-k metal gate stack. NH 3 ashing is proposed as an alternative to O 2 ashing to improve the gate-edge profile. It was found that NH 3 ashing suppresses bottom oxide growth below the thin HfO 2 layer, reducing Si recesses in the source/drain active area, and eliminating bottom oxide encroachment into the gate edge. The NH 3 ashing process also makes the HfO 2 film more resistant to the wet chemistry, which reduces the high-k undercut beneath the metal gate during the high-k removal process.

Impact of Metal Gate Deposition Method on Characteristics of Gate-First MOSFET with Hf-Silicate

This paper compares metal oxide semiconductor field effect transistor MOSFET characteristics of TiN metal gate deposited by atomic layer deposition ALD and chemical vapor deposition CVD on Hf-based high-k dielectrics. Despite many similarities between these two techniques, clear differences were found in device characteristics such as equivalent oxide thickness EOT , mobility, dopant diffusion, and trap generation. ALD TiN results in a thicker EOT than CVD TiN due to its inherent purging cycle and higher process temperature, but it has a stronger resistance to dopant diffusion. The ALD TiN process also provides better interfacial characteristics, thus better device performance.

Impact of Metal Wet Etch on Device Characteristics and Reliability for Dual Metal Gate/High-k CMOS

This paper presents a comparative study of the impact of metal wet etch on carrier mobility and metal gate/high-k device characteristics and reliability. A TaSiN metal wet etch process that is highly selective to the underlying HfO2 dielectric has been developed. While the metal wet etch slightly degraded the electron mobility, it did not affect hole mobility. It did not show any effect on fast transient charge trapping, and, in fact, improved negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI)

Morphology and Crystallization of Ultrathin HfON ( EOT ⩽ 1 nm ) with TiN Metal Gate Impact on Electron Mobility

The microstructural morphology and crystallization kinetics of ultrathin HfON with different thicknesses (equivalent oxide thickness, EOT) have been studied in terms of their influence on electron mobility. Cross-sectional and plan-view transmission electron microscopy showed that crystallization is significantly suppressed when HfON was less than 2 nm thick. Thinner HfON enhances electron mobility because of less transient charge trapping. Ultrathin HfON with an amorphous phase shows improved mobility, probably due to less remote coulomb scattering in addition to the absence of transient charge trapping.