T. D. Loveless

Phase-Dependent Single-Event Sensitivity Analysis of High-Speed A/MS Circuits Extracted from Asynchronous Measurements

A method for experimental determination of the phase dependence of single-event sensitivity in high-speed A/MS circuits is presented. The technique ensures testing coverage of the complete data cycle and results in a correlation of errors to the data or clock cycle of the circuit. Designers can apply the information, along with knowledge of the circuit state at the time of errors, to make informed radiation-hardening-by-design decisions.

Radiation Hardening of Voltage References Using Chopper Stabilization

A technique for enhancing the precision of voltage references in an ionizing radiation environment is presented. Radiation-induced mismatch is identified as a fundamental source of error in voltage reference topologies, and chopper offset cancellation is used to mitigate the effect. The efficacy of the proposed technique is demonstrated by irradiating test chips fabricated in a commercial 180-nm process.

BasketBallBot: Developing an intelligent controls teaching platform using LabView, MATLAB, and Arduino

Fuzzy logic seeks to express human modes of reasoning and decision making in a mathematical form. This is evident in its terminology such as “linguistic variables” defined over a “universe of discourse”. By taking human expressions such as “very high” or “pretty cold” and defining them in a mathematical context, expert operator knowledge can be transferred from verbal descriptions into automated control algorithms regardless of the operators familiarity with control systems. Because fuzzy logic is designed to be easily comparable with human thought, it makes an excellent first exposure to control systems concepts to high school and undergraduate students. This project demonstrates how a complete fuzzy inference system can be constructed using educational tools already in the hands of high school students throughout the country through the FIRST (For Inspiration and Recognition of Science and Technology) competitions. This work combines data from several sensors (encoders, camera vision and ultrasonic ranging) to control a robot to aim and shoot a basketball through a hoop.

Estimating Single-Event Logic Cross Sections in Advanced Technologies

Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and single-event transient (SET) pulse widths shrink to widths on the order of the setup-and-hold time of flip-flops, the probability of latching an SET as an SEU must be reevaluated. In this paper, previous assumptions about the relationship of SET pulsewidth to the probability of latching an SET are reconsidered and a model for transient latching probability has been developed for advanced technologies. A method using the improved transient latching probability and SET data is used to predict logic SEU cross section. The presented model has been used to estimate combinational logic SEU cross sections in 32-nm partially depleted silicon-on-insulator (SOI) technology given experimental heavy-ion SET data. Experimental SEU data show good agreement with the model presented in this paper.

Time-Domain Modeling of All-Digital PLLs (ADPLLs) to Single-Event Upset (SEU) Perturbations

A uniform technology-agnostic time-domain model for both linear and nonlinear all-digital phase-locked loops (ADPLLs) is presented. This time-domain model can be used for single-event upset (SEU)-induced perturbation time prediction and SEU sensitivity characterization of common ADPLL topologies. The model is validated against field-programmable gate array-based fault injection experiments and two photon absorption laser experimental results on three different types of designs. The model is applicable to rad-harden by design activities, failure mode predictions, and general ADPLL design optimizations.

Persistent Laser-Induced Leakage in a 20 nm Charge-Pump Phase-Locked Loop (PLL)

A persistent loss-of-lock error was experimentally observed in a 20 nm charge-pump phase-locked loop (PLL). Through circuit modeling and simulation, the observed error was attributed to a non-recoverable off-state leakage increase resulted from two-photon absorption (TPA) laser-induced damage. The laser-induced damage is consistent with results from 28 nm bulk transistors.

Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology

A 20.4 GHz VCO with a tuning range of 610 MHz (3%) was designed and fabricated in a 32 nm CMOS silicon-on-insulator technology. At 36 °C, the VCO achieves an output power of 0.1 dBm and a phase noise of −99 dBc/Hz at 1 MHz offset from the center frequency. TID experiments on the VCO operating at 36 °C, 75 °C, and 100 °C show degradation in frequency, output power, and phase noise. At 100 °C and 500 krad(SiO2), the VCO shows a worst-case degradation of 630 MHz, 4.3 dBm, and 6.1 dBc/Hz in center frequency, output power, and phase noise, respectively. At 36 °C and up to 500 krad(SiO2), the VCO can be retuned to operate at the required center frequency of 20.4 GHz. However, at 100 °C, the combined effects of temperature and TID result in specification failure. The system-level impact of TID-induced degradation on VCO performance is discussed using a phase-locked loop (PLL) as an example application. Measured performance corroborates previous predictions and highlights the importance of combined effects testing for advanced RF design characterization and qualification.

Hardware based empirical model for predicting logic soft error cross-section

This work presents a technique to estimate logic cross-section using measured single-event transient pulse widths from radiation experiments. The results are verified by comparing against direct measurement of logic cross-section using C-CREST circuit. Since the logic cross-section is extracted based on experimentally measured transients, it includes device/layout level effects and could be used by existing software-based methods to accurately predict logic soft error rate.