S. Kawai

A 2/3-inch 2 M-pixel IT-CCD image sensor with individual p-wells for separate V-CCD and H-CCD formation

This 2/3-inch optical-lens-format, 2 M-pixel interline-transfer (IT) CCD image sensor achieves large charge handling capability in the vertical CCD (V-CCD), and at the same time ensures sufficient transfer efficiency in the horizontal CCD (H-CCD). A V-CCD/H-CCD connection eliminates the potential barrier caused by separate V-CCD/H-CCD formation. Image sensor performance includes a 40 k-electron charge-handling capability in the V-CCD, leading to a 71 dB dynamic range, and sufficient transfer efficiency in the H-CCD, with no deterioration in V-CCD to H-CCD transfer efficiency. The power consumption is 0.49 W, just 22% of that previously achieved in a 1-inch 2 M pixel frame interline transfer (FIT) CCD. This is possible because the p-well reduces the driving pulse amplitude in the V-CCD and the IT scheme decreases electrode capacitance and driving frequency.<<ETX>>

A 1/4 inch 380 k pixel IT-CCD image sensor employing gate-assisted punchthrough read-out mode

A newly developed 1/4-inch 380 k pixel IT-CCD image sensor features a novel cell structure in which signal charges are read out from a photodiode (PD) to a vertical-CCD (V-CCD) in a gate-assisted punchthrough mode. The cell structure, fabricated through the use of high energy ion implantation technology, enables both deep PD formation and transfer-gate (TG)/channel-stop (CS) length reduction. Deep PD formation helps increase sensitivity per PD unit area, and TG/CS length reduction widens both PD and V-CCD areas. Although the cell size is small (4.8 /spl mu/m (H)/spl times/5.6 /spl mu/m (V)), the sensor achieves both high sensitivity (35 mV/lx) and a high saturation signal (600 mV). >

Thermionic-emission-based barrier height analysis for precise estimation of charge handling capacity in CCD registers

In designing charge-coupled device (CCD) image sensors, it is essential to be able to estimate charge handling capacity. Because electrons have thermal energy, storing electrons in a well in a CCD register requires a sufficient potential barrier height to keep them from overflowing. As the quantity of electrons in a well depends on the barrier height, knowledge of this height is indispensable for precise estimation of the charge handling capacity. The authors have derived an expression describing the barrier height on the basis of thermionic emission, assuming current coefficient I/sub 0/ and well capacitance C. We derived the current coefficient I/sub 0/ and well capacitance C with computer simulations and from the results estimate the magnitude of the barrier height for a typical Vertical-CCD (V-CCD) structure. We have also examined barrier height dependence on structural parameters. Finally, we determined the barrier heights experimentally, and our results support the values obtained in the simulation.

Optical limitations to cell size reduction in IT-CCD image sensors

We have determined the practical limits of cell size reduction in interline-transfer CCD image sensors, limits resulting from diffraction occurring at the aperture above the photodiode. We have found that image cell size cannot be reduced to a level for which aperture width would fall below about 0.2 /spl mu/m. We have also found, however, that image cells with greater than 0.2 /spl mu/m aperture size are sensitive over the entire wavelength range of visible light, and that sensitivity can be increased by thinning the photoshield film.

Photo response analysis in CCD image sensors with a VOD structure

Photo response in CCD image sensors with Vertical-Overflow-Drain (VOD) was analyzed in an attempt to discover a way to lessen the photo response rise that accompanies increasing incident light intensity in the saturation region. A photo response analysis based on transistor I-V characteristics revealed that the extent of rise in the saturation region is uniquely determined by the non-ideality factor and temperature. Calculation of the non-ideality factor and its dependence on P-well impurity concentration and layer thickness further revealed that fabrication of P-wells with lower impurity concentrations and thicker layers would be effective in suppressing photo response rise. >

A 1/2-in 1.3 M-pixel progressive-scan IT-CCD for digital still camera applications

A 1/2-in 1.3 M-pixel progressive-scan interline-transfer charge-coupled-device (IT-CCD) image sensor has been developed for small, low-power mega-pixel digital still cameras (DSCs). The pixel size as small as 5 /spl mu/m square makes small-size progressive-scan IT-CCD (8.3/spl times/7.1 mm/sup 2/) for the SXGA format. A two-phase-drive horizontal-CCD with phosphorus-implanted storage regions helps reduce the driving voltage to 2.5 V, resulting in the power consumption of the device being as low as 146 mW. A new source-follower amplifier with separate p-well driver transistors achieves 12% higher gain than that obtained using a conventional amplifier. An overflow drain with a self-adjusting potential barrier can instantly remove superfluous charges in vertical-CCDs just before an exposure period, which enables DSCs to perform such functions as quick auto-focusing and dark-current removal. New dual operation modes for still and motion pictures can provide not only high-resolution color signals in a 15-frame/s 1050-line progressive mode but also wide-dynamic-range color signals in a 30-frame/s 525-line progressive mode. The latter mode employs a pixel-exchange-and-mix readout operation that helps halve the number of scanning lines with no loss in sensitivity and color information.

A 1/2 inch 1.3 M-pixel progressive-scan IT-CCD for still and motion picture applications

For still pictures, the sensor provides high-resolution color signals in a 15 frame/s 1050-line progressive mode. For motion pictures, it provides wide-dynamic range color signals in a 30 frame/s 525-line progressive mode. This latter mode employs a pixel-exchange-and-mix readout function that helps halve the number of scanning lines. A 5/spl times/5 /spl mu/m/sup 2/ pixel makes the 8.3/spl times/7.1 mm/sup 2/ IT-CCD the smallest yet applicable to the SXGA format. A two-phase drive horizontal CCD with phosphorus-implanted storage regions (PST-HCCD) with optimized wells so that they do not generate potential pockets under inter-electrode gaps helps reduce the driving voltage to 2.5 V. In still camera use, an overflow drain with self-adjusting potential barrier (SA-OFD) is attached to the HCCD to remove superfluous charges in the vertical CCD (VCCD) just before an exposure. A source-follower amplifier with separate p-well driver transistors with suppressed back-gate effects achieves a gain 11% higher than that obtained using a conventional amplifier. Green-sensitivity of the device is 190 mV (F8, 706 nt, 1/30 s), and the saturation signal is 400 mV (1050-line progressive mode).

Dynamic range improvement by narrow-channel effect suppression and smear reduction technologies in small pixel IT-CCD image sensors

Technologies for narrow-channel effect suppression in photodiodes (PDs) and vertical CCDs (V-CCDs) and for smear reduction in PDs have been developed in order to improve dynamic range in small pixel interline-transfer CCD (IT-CCD) image sensors. The new technologies have been applied to a progressive-scan IT-CCD image sensor with 5 /spl mu/m square pixels and have (1) increased the charge handling capability of its V-CCDs to 4500 electrons/V; (2) improved its smear value to -95 dB; and (3) increased the saturation charge of its PDs to 2.3/spl times/10/sup 4/ electrons.

1-million-pixel progressive-scan 60-fps IT-CCD image sensor

A 1M-pixel progressive-scan interline-transfer CCD image sensor has been developed.It features high resolution, real- time speed and square pixels. A real-time speed was obtained by a pair of H-CCDs, located at the upper and lower of the image area and driven at 43MHz. Charges of the upper and lower halves of the image area are output separately by using the upper and lower H-CCDs, respectively. This operation enables a 1024 by 1024 progressive scan at 60 frame/sec. The device can be operated in a 512 by 512 progressive scan at 120 frame/sec by combining the charges in each of two vertically-adjacent pixels and two horizontally-adjacent pixels. Furthermore, a 1024 by 1024 interlace scan at 120 field/sec is also acceptable for either frame-integration or field-integration. The device can also be operated in a 1024 by 1024 progressive scan at 30 frame/sec by using only one of the H-CCD.