S. Montusclat

0.13

This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.

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This paper presents a complete 0.13 mum SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2fF/mum2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors.

m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

Today, SiGe HBT and MOSFET cut-off frequencies are higher than 230 GHz (Chevalier et al., 2004) and this increase allows new millimeter wave (MMW) applications on silicon such as 60 GHz WLAN and 77 GHz automotive radar. This study focuses on a wireless communication block with the antenna integration. Functions such as amplifier and filter have been used to perform this block. This is a demonstration of individual component integration and co-integration with antenna/LNA matching. Antenna achieved on advanced sub 120nm HCMOS high resistivity silicon on insulator (HR SOI) (p >1 kOhms.cm) has been designed and integrated. A low noise amplifier (LNA) and a filter have been retained for this first chain. Antenna and block characterizations are led on a dedicated on-wafer test bench. Antenna performances in term of gain and radiation pattern are given. A communication link has been then established between a single antenna (-2 dB gain) and the full communication block with a -19 dB transmission gain at 40 GHz

0.13μm SiGe BiCMOS technology for mm-wave applications

Silicon-based technology is now able to address new applications such as Wireless HDMI. Performances of CMOS and BiCMOS transistors enable RF designers to integrate the entire front-end. The last building block of the integration is the antenna. A folded-slot antenna and 4-antenna linear array layouts on HR SOI silicon using standard CMOS process BEOL are described. In this paper, return loss and gain measurements are performed on both structures to show the interest of an array to improve the global performances of the RF chain. The measured gain is increased from -4.7 dBi (folded-slot) to -1.8 dBi (4-element array), which is compatible with a 2 meter wireless link at 60 GHz. Moreover, an antenna radiation pattern measurement setup which is at the R&D State-of-the-Art is described and exploited for extracting radiation patterns from on-silicon mmWave antennas.

Silicon full integrated LNA, filter and antenna system beyond 40 GHz for MMW wireless communication links in advanced CMOS technologies

Today, SiGe HBT cut-off frequencies are higher than 230 GHz (P. Chevalier, et al., 2004) and this increase allows new millimeter wave (MMW) applications on silicon such as 60 GHz WLAN and 77 GHz automotive radar. One of the success keys is then the passive integration. This study focuses on a 52 GHz silicon integrated antenna and related feeding transmission line (TL) topics. Double slot antenna integrated in a standard BiCMOS process and 40 GHz coplanar patch antenna (2.3 dB gain @ 40 GHz) with a coplanar waveguide (CPW) feed line are depicted and characterized. Integrated TL achieved on standard STMicroelectronics (ST) BiCMOS, CMOS and silicon on insulator (SOI) technologies are described, performances are given (<0.7 dB/mm losses @ 80 GHz for SOI CPW). A full modeling has been developed up to 80 GHz with new approach for CPW on silicon technology due to passivation layer

Folded-Slot Integrated Antenna Array for Millimeter-Wave CMOS Applications on Standard HR SOI Substrate

This paper presents high-Q and high-inductance-density on-chip inductors made on high resistivity (HR) substrate using STMicroelectronics LP 65 nm SOI CMOS technology with 6 copper metal layers. For the first time, on-chip inductor architectures dedicated to HR SOI CMOS technology are reported and benchmarked with current one used in standard RF CMOS technologies. According to the measurement results, proposed 3D HR SOI inductor occupies only 50% of the area of the conventional planar spiral inductor with the same inductance and similar quality factor. By virtue of the small area consumed by those 3D inductors, the size and cost of the radio frequency (RF) chip integrated on HR SOI can be significantly reduced in comparison with standard bulk technology which reenforces the advantage of SOI technology for RF applications.

Silicon integrated antenna developments up to 80 GHz for millimeter wave wireless links

Integrated antenna on-wafer measurements, achieved on standard STMicroelectronics BiCMOS and glass processes, are presented for applications between 40 GHz and 80 GHz. Radiation pattern and S-parameter measurements of a dipole and a patch antenna are described. For the first time, measurements of integrated millimeterwave antennas are shown at these frequencies. A complete test bench has been realized. In addition, associated wideband high frequency dipole modeling is described.

Integrated Inductors in HR SOI CMOS technologies: on the economic advantage of SOI technologies for the integration of RF applications

During past years, High Resistivity (HR) SOI CMOS technology has emerged as a promising one for the integration of RF applications, mainly because of the improvement of passive component related to HR substrate. This paper summarizes, for the first time, an in depth analysis of different optimization scheme suitable for on-chip inductors fabricated on HR substrate, using advanced 65 nm SOI CMOS technology with 6 copper metal levels. Measurement results demonstrated that proposed optimized SOI inductor architectures, integrated in a standard advanced digital back-end of line (BEOL), could address high quality factor (single ended quality factor greater than 20), have high current capability (up to 260 mA @ 125degC) or could enable a huge area saving (up to 50 %).

On-wafer radiation pattern measurements of integrated antennas on standard BiCMOS and glass processes for 40-80GHz applications

Today, measurement of 65 nm CMOS and 130 nm-based SiGe HBTs technologies demonstrate both Ftau (current gain cut-off frequency) and Fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100 nm III-V HEMT. Consequently, the integration of full transceiver at 60 GHz has been achieved both in SiGe bipolar and CMOS technology. In the same time passive circuits working at 220 GHz have been achieved and characterized on high resistivity SOI demonstrating state-of-the-art performances and good agreement with electrical simulations using developed models. Moreover, HR SOI has also demonstrated some advantages concerning the performances of integrated antennas and a first fully integrated prototype with amplifier, filter and antenna has already been achieved using STMicroelectronics 130 nm CMOS HR SOI technology. This paper will review the MMW performances of STMicrolectronics 65 nm CMOS HR SOI technology from device up to circuit level and discuss the opportunities of MMW SoC integrated on CMOS HR SOI technology.

On the Design of High Performance RF Integrated Inductors on High Resistively Thin Film 65 nm SOI CMOS Technology

This paper focuses on an integrated fractal antenna on HR SOI silicon substrate. The antenna is based on a double-slotted dipole antenna. A technology overview is provided in the first section. Then the concerned designed resonant structures are depicted and compared. Simulations are performed on Ansoft HFSS 3D electromagnetic software, and measurements are completed with an on-wafer test bench.