Safak Sayan

Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS

In this paper, we present a design and benchmarking methodology of Spin Wave Device (SWD) circuits based on micromagnetic modeling. SWD technology is compared against a 10nm FinFET CMOS technology, considering the key metrics of area, delay and power. We show that SWD circuits outperform the 10nm CMOS FinFET equivalents by a large margin. The area-delay-power product (ADPP) of SWD is smaller than CMOS for all benchmarks from 2.5× to 800×. On average, the area of SWD circuits is 3.5× smaller and the power consumption is two orders of magnitude lower compared to the 10nm CMOS reference circuits.

Spintronic majority gates

In this paper we present an overview of two types of majority gate devices based on spintronic phenomena. We compare the spin torque majority gate and the spin wave majority gate and describe work on these devices. We discuss operating conditions for the two device concepts, circuit implication and how these reflect on materials choices for device implementation.

Overview of spin-based majority gates and interconnect implications

In this paper we review majority gate devices based on spintronic phenomena. We focus the discussion on spin wave majority gates and report on benchmarking and place and route experiments for these devices. We find that these devices could help not only reduce power consumption, but in certain instances also reduce the amount of wiring required compared to the CMOS equivalent.

Graphene wires as alternative interconnects

In this paper, we evaluate the material properties of graphene and compare with Cu in order to assess the potential application of graphene to replace copper wires in BEOL interconnects. Based on circuit and system-level simulations, high restrictions are imposed to graphene with respect to contact resistance and mean free path. Experimentally we measure, a mean-free-path (MFP) of ~150 nm, which exceeds the value for Cu. However, contact engineering will be the key issue for integration of graphene as interconnect.

WS 2 transistors on 300 mm wafers with BEOL compatibility

For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or atomic layer deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al2O3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.