Saurabh Saxena

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH

This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. In addition to the stage-sharing scheme, other changes are introduced to improve the modulator dynamic range (DR) and power dissipation. Measurement results show that the modulator designed in a 0.13 μm CMOS technology achieves 75 dB SNDR over a 5 MHz signal bandwidth with a clock frequency of 130 MHz, while dissipating less than 9 mW analog power.

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In this paper, we present a time-based equalization scheme to implement transmit de-emphasis in voltage-mode drivers. Using two-level pulse-width modulation, this work decouples the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers using voltage-based de-emphasis. A prototype PWM-based 5 Gb/s voltage-mode transmitter was implemented in a 90 nm CMOS process and characterized across different channels and output swings. The horizontal/vertical eye opening (BER=10-12) at the end of 60 and 96 in stripline channels is 78 mv/0.6 UI and 8 mV/0.3 UI, respectively. Duty cycle distortion of the clock severely reduced the margins, so the overall performance can be improved by applying duty-cycle correction to clock signals. The transmitter consumes a total power 15.6 mW of which 2.5 mW is consumed in the digital PLL and 7.8 mW in the pre-/output drivers and regulators. This translates to a power efficiency of 3.1 mW/Gb/s, which compares favorably with the state of the art.

Modulator Dissipating 16 mW Power

A reference-less half-rate digital clock and data recovery (CDR) circuit employing a phase-rotating phase-locked loop (PRPLL) as phase interpolator is presented. By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain. Fabricated in a 90 nm CMOS process, the prototype CDR achieves error-free operation (BER <; 10-12) with PRBS data sequences ranging from PRBS7 to PRBS31. At 5 Gb/s, it consumes 13.1 mW power and achieves a recovered clock long-term jitter of 5.0 ps rms/44.0 ps pp when operating with PRBS31 input data. The measured JTRAN bandwidth is 2 MHz and JTOL corner frequency is 16 MHz. The CDR is tolerant to 110 mV pp of sinusoidal noise on the DCO supply voltage at the worst case noise frequency of 7 MHz. At 2.5 GHz, the PRPLL consumes 2.9 mW and achieves -134 dBc/Hz phase noise at 1 MHz frequency offset. The differential and integral non-linearity of its digital-to-phase transfer characteristic are within ±0.2 LSB and ±0.4 LSB, respectively.

A 5 Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis

Modern systems-on-chips (SoCs) perform many diverse analog, digital, and mixed-signal functions. They contain a wide variety of modules such as multicore processors, memories, I/O interfaces, power management, and wireless transceivers. Each module has its own unique clock requirements to maximize the overall system performance. For example, dynamic frequency scaling (DFS) saves processor power, spread spectrum clocking (SSC) reduces electromagnetic interference (EMI), and rapid power cycling between idle and active states allows energy-proportional operation. A conventional analog integer-N phase-locked loop (PLL)-based clock generation unit (CGU) occupies large area, has a long lock time, and its output frequency resolution is limited by the reference clock frequency. While the digital fractional-N PLL-based CGU in [1] overcomes some of these drawbacks, it suffers from an intrinsic tradeoff between the time-to-digital converter (TDC)/fractional-divider quantization error and oscillator phase noise. As a result, it requires either a high-resolution TDC or a low-noise oscillator both of which incur power penalty. Further, narrow PLL bandwidth limits SSC modulation frequency and increases lock time making it unsuitable for energy-proportional operation. Open-loop frequency generation using direct-digital synthesis (DDS) overcomes the drawbacks of closed-loop PLLs but it consumes a significant amount of power [2]. This paper presents an all-digital CGU using open-loop fractional dividers. Unlike [1], the proposed CGU, using only one integer-N PLL and a single reference clock, can provide multiple low-jitter outputs over a wide frequency range with fine frequency resolution. It also has SSC capability with programmable modulation depth and achieves instantaneous frequency switching.

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop

A VCO-based MASH delta-sigma ADC architecture is introduced that uses multi-rating of the two stages. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. To demonstrate this architecture, a prototype consisting of a first-order switched-capacitor (SC) integrator with a 4-bit quantizer operating at 100MHz is followed by a second-stage VCO-based ADC operating at 1.2GHz. The chip is implemented in a 130nm 1P8M CMOS process. The measured SNDR is 77dB for a 4MHz signal bandwidth with a power consumption of 13.8mW from a 1.3V supply. The resulting FoM is 298fJ per conversion.

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS

A novel MASH delta-sigma (ΔΣ) ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

Continuous-rate clock-and-data recovery (CDR) circuits with automatic frequency acquisition offer flexibility in both optical and electrical communication networks, and minimize cost with a single-chip multi-standard solution. The two major challenges in the design of such a CDR are: (a) extracting the bit-rate from the incoming random data stream, and (b) designing a wide-tuning-range low-noise oscillator. Among all available frequency detectors (FDs), the stochastic divider-based approach has the widest frequency acquisition range and is well suited for sub-rate CDRs [1]. However, its accuracy strongly depends on input transition density (0 ≤ ρ ≤ 1), with any deviation of ρ from 0.5 (50% transition density) causing 2×(ρ-0.5)×106 ppm of frequency error. In this paper, we present an automatic frequency-acquisition scheme that has unlimited range and is immune to variations in transition density. Implemented using a conventional bang-bang phase detector (BBPD), it requires minimum additional hardware and is applicable to sub-rate CDRs as well. Instead of using multiple LC oscillators that are carefully designed to cover a wide frequency range [2,3], a ring-oscillator-based fractional-N PLL is used as a digitally controlled oscillator (DCO) to achieve both wide range and low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring-oscillator-noise suppression.

A 12.5-bit 4 MHz 13.8 mW MASH

A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. The proposed automatic frequency acquisition scheme implemented using a conventional bang-bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition density, and is applicable to subrate CDRs. A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs. The CDR is implemented using a digital D/PLL architecture to decouple JTRAN bandwidth from jitter tolerance (JTOL) corner frequency, eliminate jitter peaking, and remove JTRAN dependence on BBPD gain. Fabricated in a 65 nm CMOS process, the prototype CDR achieves error-free operation (BER <; 10-12) from 4 to 10.5 Gb/s with pseudorandom binary sequence (PRBS) data sequences ranging from PRBS7 to PRBS31. The proposed automatic frequency acquisition scheme always locks the CDR loop within 1000 ppm residual frequency error in worst case. At 10 Gb/s, the CDR consumes 22.5 mW power and achieves a recovered clock long-term jitter of 2.2 psrms/24.0 pspp with PRBS31 input data. The measured JTRAN bandwidth and JTOL corner frequencies are 0.2 and 9 MHz, respectively.

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Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoMJ) that quantifies the power-jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0-5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 psrms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoMJ is -228.5 dB, which is the best among all reported ring-based FNPLLs.

Modulator With Multirated VCO-Based ADC

Energy-proportional operation of serial links is imperative for realizing energy-efficient data centers and low-power mobile interfaces such as MIPI. Burst-mode communication, where the link is powered-off when idle and powered-on when needed, achieves energy proportional operation. Ideally, a burst mode link must be turned on/off in zero time, must consume zero power in the off-state and must incur zero energy overhead while making on/off transitions. However, these requirements are difficult to meet in practice and as a consequence, the efficacy of burst mode communication in achieving energy proportional operation is reduced. The main challenges in achieving small power-on time and off-state power include the design of fast-locking PLLs, CDRs and achieving fast settling of bias node voltages. In this paper, we present a complete 7Gb/s energy-proportional embedded-clock transceiver that achieves less than 20ns power-on time while consuming 63.7mW on-state power, 0.74mW off-state power and 1.2nJ of total transition energy penalty per burst.